2018-12-14 15:16:49 +00:00
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#ifndef __VCOREIII_H
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#define __VCOREIII_H
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#include <linux/sizes.h>
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/* Onboard devices */
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_INIT_SP_OFFSET 0x400000
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2018-12-14 15:16:49 +00:00
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2022-11-16 18:10:28 +00:00
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#define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
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2018-12-14 15:16:49 +00:00
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2022-11-16 18:10:37 +00:00
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#define CFG_SYS_SDRAM_BASE 0x80000000
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2018-12-14 15:16:49 +00:00
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#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
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2022-11-16 18:10:37 +00:00
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#define CFG_SYS_SDRAM_SIZE (128 * SZ_1M)
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2018-12-14 15:16:49 +00:00
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#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT)
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2022-11-16 18:10:37 +00:00
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#define CFG_SYS_SDRAM_SIZE (256 * SZ_1M)
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2018-12-14 15:16:49 +00:00
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#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16)
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2022-11-16 18:10:37 +00:00
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#define CFG_SYS_SDRAM_SIZE (512 * SZ_1M)
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2018-12-14 15:16:49 +00:00
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#else
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#error Unknown DDR size - please add!
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x81000000\0" \
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"spi_image_off=0x00100000\0" \
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"console=ttyS0,115200\0" \
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"setup=setenv bootargs console=${console} ${mtdparts}" \
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"${bootargs_extra}\0" \
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"spiboot=run setup; sf probe; sf read ${loadaddr}" \
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"${spi_image_off} 0x600000; bootm ${loadaddr}\0" \
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"ubootfile=u-boot.bin\0" \
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"update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};" \
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"sf erase UBoot 0x100000;" \
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"sf write ${loadaddr} UBoot ${filesize}\0" \
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"bootcmd=run spiboot\0" \
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""
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#endif /* __VCOREIII_H */
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