mirror of
https://github.com/AsahiLinux/u-boot
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MSCC: add board support for the Ocelots based evaluation boards
Adding the support for 2 boards sharing common code for Ocelot chip: PCB120 and PCB123 Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
parent
6bd8231a6d
commit
6787c1ece0
12 changed files with 510 additions and 0 deletions
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@ -518,6 +518,11 @@ M: Lars Povlsen <lars.povlsen@microchip.com>
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M: Horatiu Vultur <horatiu.vultur@microchip.com>
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S: Maintained
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F: arch/mips/mach-mscc/
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F: arch/mips/dts/mscc*
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F: arch/mips/dts/ocelot*
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F: board/mscc/
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F: configs/mscc*
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F: include/configs/vcoreiii.h
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MMC
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M: Jaehoon Chung <jh80.chung@samsung.com>
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152
arch/mips/dts/mscc,ocelot.dtsi
Normal file
152
arch/mips/dts/mscc,ocelot.dtsi
Normal file
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@ -0,0 +1,152 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mscc,ocelot";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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device_type = "cpu";
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clocks = <&cpu_clk>;
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reg = <0>;
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};
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};
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aliases {
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serial0 = &uart0;
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};
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cpuintc: interrupt-controller@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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cpu_clk: cpu-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <500000000>;
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};
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ahb_clk: ahb-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <250000000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x70000000 0x2000000>;
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interrupt-parent = <&intc>;
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cpu_ctrl: syscon@0 {
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compatible = "mscc,ocelot-cpu-syscon", "syscon";
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reg = <0x0 0x2c>;
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};
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intc: interrupt-controller@70 {
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compatible = "mscc,ocelot-icpu-intr";
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reg = <0x70 0x70>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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uart0: serial@100000 {
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pinctrl-0 = <&uart_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x100000 0x20>;
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interrupts = <6>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: serial@100800 {
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pinctrl-0 = <&uart2_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x100800 0x20>;
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interrupts = <7>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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spi0: spi-master@101000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-ssi";
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reg = <0x101000 0x40>;
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num-chipselect = <4>;
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bus-num = <0>;
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reg-io-width = <4>;
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reg-shift = <2>;
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spi-max-frequency = <18000000>; /* input clock */
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clocks = <&ahb_clk>;
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status = "disabled";
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};
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reset@1070008 {
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compatible = "mscc,ocelot-chip-reset";
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reg = <0x1070008 0x4>;
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};
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gpio: pinctrl@1070034 {
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compatible = "mscc,ocelot-pinctrl";
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reg = <0x1070034 0x68>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 22>;
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uart_pins: uart-pins {
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pins = "GPIO_6", "GPIO_7";
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function = "uart";
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};
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uart2_pins: uart2-pins {
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pins = "GPIO_12", "GPIO_13";
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function = "uart2";
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};
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spi_cs1_pin: spi-cs1-pin {
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pins = "GPIO_8";
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function = "si";
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};
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spi_cs2_pin: spi-cs2-pin {
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pins = "GPIO_9";
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function = "si";
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};
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spi_cs3_pin: spi-cs3-pin {
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pins = "GPIO_16";
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function = "si";
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};
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spi_cs4_pin: spi-cs4-pin {
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pins = "GPIO_17";
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function = "si";
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};
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};
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};
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};
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42
arch/mips/dts/mscc,ocelot_pcb.dtsi
Normal file
42
arch/mips/dts/mscc,ocelot_pcb.dtsi
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@ -0,0 +1,42 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/dts-v1/;
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#include "mscc,ocelot.dtsi"
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/ {
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compatible = "mscc,ocelot";
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aliases {
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spi0 = &spi0;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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pinctrl-0 = <&spi_cs1_pin>;
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pinctrl-names = "default";
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spi-flash@0 {
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compatible = "spi-flash";
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spi-max-frequency = <18000000>; /* input clock */
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reg = <0>; /* CS0 */
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};
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spi-nand@1 {
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compatible = "spi-nand";
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spi-max-frequency = <18000000>; /* input clock */
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reg = <1>; /* CS1 */
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};
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};
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12
arch/mips/dts/ocelot_pcb120.dts
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12
arch/mips/dts/ocelot_pcb120.dts
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@ -0,0 +1,12 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/dts-v1/;
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#include "mscc,ocelot_pcb.dtsi"
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/ {
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model = "Ocelot PCB120 Reference Board";
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compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
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};
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12
arch/mips/dts/ocelot_pcb123.dts
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12
arch/mips/dts/ocelot_pcb123.dts
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@ -0,0 +1,12 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/dts-v1/;
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#include "mscc,ocelot_pcb.dtsi"
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/ {
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model = "Ocelot PCB123 Reference Board";
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compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
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};
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@ -79,4 +79,6 @@ config DDRTYPE_MT47H128M8HQ
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endchoice
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source "board/mscc/ocelot/Kconfig"
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endmenu
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14
board/mscc/ocelot/Kconfig
Normal file
14
board/mscc/ocelot/Kconfig
Normal file
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@ -0,0 +1,14 @@
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# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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config SYS_VENDOR
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default "mscc"
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if SOC_OCELOT
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config SYS_BOARD
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default "ocelot"
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config SYS_CONFIG_NAME
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default "ocelot"
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endif
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4
board/mscc/ocelot/Makefile
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4
board/mscc/ocelot/Makefile
Normal file
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@ -0,0 +1,4 @@
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# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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obj-$(CONFIG_SOC_OCELOT) := ocelot.o
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58
board/mscc/ocelot/ocelot.c
Normal file
58
board/mscc/ocelot/ocelot.c
Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <environment.h>
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#include <spi.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define MSCC_GPIO_ALT0 0x54
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#define MSCC_GPIO_ALT1 0x58
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void external_cs_manage(struct udevice *dev, bool enable)
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{
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u32 cs = spi_chip_select(dev);
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/* IF_SI0_OWNER, select the owner of the SI interface
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* Encoding: 0: SI Slave
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* 1: SI Boot Master
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* 2: SI Master Controller
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*/
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if (!enable) {
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writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
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ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), BASE_CFG + ICPU_SW_MODE);
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clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
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ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
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ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
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} else {
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writel(0, BASE_CFG + ICPU_SW_MODE);
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clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
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ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
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ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
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}
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}
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void board_debug_uart_init(void)
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{
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/* too early for the pinctrl driver, so configure the UART pins here */
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setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(6) | BIT(7));
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clrbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT1, BIT(6) | BIT(7));
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}
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int board_early_init_r(void)
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{
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/* Prepare SPI controller to be used in master mode */
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writel(0, BASE_CFG + ICPU_SW_MODE);
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clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
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ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
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ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
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/* Address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
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return 0;
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}
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67
configs/mscc_ocelot_defconfig
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67
configs/mscc_ocelot_defconfig
Normal file
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@ -0,0 +1,67 @@
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CONFIG_MIPS=y
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CONFIG_SYS_TEXT_BASE=0x40000000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_DEBUG_UART_BOARD_INIT=y
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CONFIG_DEBUG_UART_BASE=0x70100000
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CONFIG_DEBUG_UART_CLOCK=250000000
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CONFIG_ARCH_MSCC=y
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CONFIG_TARGET_OCELOT_PCB123=y
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CONFIG_SYS_LITTLE_ENDIAN=y
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CONFIG_DEBUG_UART=y
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CONFIG_FIT=y
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CONFIG_BOOTDELAY=3
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200"
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CONFIG_LOGLEVEL=7
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_SYS_PROMPT="pcb123 # "
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# CONFIG_CMD_BDI is not set
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# CONFIG_CMD_CONSOLE is not set
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# CONFIG_CMD_ELF is not set
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# CONFIG_CMD_EXPORTENV is not set
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# CONFIG_CMD_IMPORTENV is not set
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# CONFIG_CMD_CRC32 is not set
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CONFIG_CMD_MD5SUM=y
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_MEMTEST=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_DHCP=y
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# CONFIG_NET_TFTP_VARS is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_CMD_PING=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)"
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CONFIG_CMD_UBI=y
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# CONFIG_CMD_UBIFS is not set
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# CONFIG_ISO_PARTITION is not set
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CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_CLK=y
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CONFIG_DM_GPIO=y
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CONFIG_MTD=y
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CONFIG_MTD_SPI_NAND=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_SPI_FLASH_MTD=y
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CONFIG_DM_ETH=y
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CONFIG_PINCTRL=y
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CONFIG_PINCONF=y
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CONFIG_DM_SERIAL=y
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_DEBUG_UART_ANNOUNCE=y
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_DESIGNWARE_SPI=y
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CONFIG_LZMA=y
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60
configs/mscc_ocelot_pcb120_defconfig
Normal file
60
configs/mscc_ocelot_pcb120_defconfig
Normal file
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CONFIG_MIPS=y
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CONFIG_SYS_TEXT_BASE=0x40000000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_ARCH_MSCC=y
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CONFIG_SYS_LITTLE_ENDIAN=y
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CONFIG_FIT=y
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CONFIG_BOOTDELAY=3
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200"
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CONFIG_LOGLEVEL=7
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_SYS_PROMPT="pcb120 # "
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# CONFIG_CMD_BDI is not set
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# CONFIG_CMD_CONSOLE is not set
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# CONFIG_CMD_ELF is not set
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# CONFIG_CMD_EXPORTENV is not set
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# CONFIG_CMD_IMPORTENV is not set
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# CONFIG_CMD_CRC32 is not set
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CONFIG_CMD_MD5SUM=y
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_MEMTEST=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_DHCP=y
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# CONFIG_NET_TFTP_VARS is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_CMD_PING=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)"
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CONFIG_CMD_UBI=y
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# CONFIG_CMD_UBIFS is not set
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# CONFIG_ISO_PARTITION is not set
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CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb120"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_CLK=y
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CONFIG_DM_GPIO=y
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CONFIG_MTD=y
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CONFIG_MTD_SPI_NAND=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_SPI_FLASH_MTD=y
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CONFIG_DM_ETH=y
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CONFIG_PINCTRL=y
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CONFIG_PINCONF=y
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CONFIG_DM_SERIAL=y
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_DESIGNWARE_SPI=y
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CONFIG_LZMA=y
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82
include/configs/vcoreiii.h
Normal file
82
include/configs/vcoreiii.h
Normal file
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@ -0,0 +1,82 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
#ifndef __VCOREIII_H
|
||||
#define __VCOREIII_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
|
||||
/* Onboard devices */
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN 0x100000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
|
||||
|
||||
#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */
|
||||
#ifdef CONFIG_SOC_LUTON
|
||||
#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333
|
||||
#else
|
||||
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
|
||||
#endif
|
||||
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
|
||||
#define CONFIG_ENV_OFFSET (1024 * 1024)
|
||||
#define CONFIG_ENV_SIZE (256 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
|
||||
|
||||
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
|
||||
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 0 /* This force to read from DT */
|
||||
#define CONFIG_ENV_SPI_MODE 0 /* This force to read from DT */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
||||
#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
|
||||
#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
|
||||
#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT)
|
||||
#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M)
|
||||
#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16)
|
||||
#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M)
|
||||
#else
|
||||
#error Unknown DDR size - please add!
|
||||
#endif
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
|
||||
#define VCOREIII_DEFAULT_MTD_ENV \
|
||||
"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
|
||||
"mtdids="CONFIG_MTDIDS_DEFAULT"\0"
|
||||
#else
|
||||
#define VCOREIII_DEFAULT_MTD_ENV /* Go away */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
VCOREIII_DEFAULT_MTD_ENV \
|
||||
"loadaddr=0x81000000\0" \
|
||||
"spi_image_off=0x00100000\0" \
|
||||
"console=ttyS0,115200\0" \
|
||||
"setup=setenv bootargs console=${console} ${mtdparts}" \
|
||||
"${bootargs_extra}\0" \
|
||||
"spiboot=run setup; sf probe; sf read ${loadaddr}" \
|
||||
"${spi_image_off} 0x600000; bootm ${loadaddr}\0" \
|
||||
"ubootfile=u-boot.bin\0" \
|
||||
"update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};" \
|
||||
"sf erase UBoot 0x100000;" \
|
||||
"sf write ${loadaddr} UBoot ${filesize}\0" \
|
||||
"bootcmd=run spiboot\0" \
|
||||
""
|
||||
#endif /* __VCOREIII_H */
|
Loading…
Reference in a new issue