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u-boot/arch/arm/dts/ast2500-u-boot.dtsi

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cosmetic: aspeed: Modify for SPDX-License Modify SPDX-License for furture patch warning Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-31 06:03:05 +00:00
// SPDX-License-Identifier: GPL-2.0
cosmetic: aspeed: ast2500: Rename clock header Rename the ast2500-scu.h to aspeed-clock.h. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2020-08-31 06:03:03 +00:00
#include <dt-bindings/clock/aspeed-clock.h>
aspeed: Device Tree configuration for Reset Driver Add Reset Driver configuration to ast2500 SoC Device Tree and bindings for various reset signals Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:25 +00:00
#include <dt-bindings/reset/ast2500-reset.h>
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
#include "ast2500.dtsi"
/ {
scu: clock-controller@1e6e2000 {
compatible = "aspeed,ast2500-scu";
reg = <0x1e6e2000 0x1000>;
dm: dts: Convert driver model tags to use new schema Now that Linux has accepted these tags, move the device tree files in U-Boot over to use them. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-13 15:56:33 +00:00
bootph-all;
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
#clock-cells = <1>;
#reset-cells = <1>;
};
aspeed: Device Tree configuration for Reset Driver Add Reset Driver configuration to ast2500 SoC Device Tree and bindings for various reset signals Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:25 +00:00
rst: reset-controller {
dm: dts: Convert driver model tags to use new schema Now that Linux has accepted these tags, move the device tree files in U-Boot over to use them. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-13 15:56:33 +00:00
bootph-all;
aspeed: Device Tree configuration for Reset Driver Add Reset Driver configuration to ast2500 SoC Device Tree and bindings for various reset signals Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:25 +00:00
compatible = "aspeed,ast2500-reset";
#reset-cells = <1>;
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
sdrammc: sdrammc@1e6e0000 {
dm: dts: Convert driver model tags to use new schema Now that Linux has accepted these tags, move the device tree files in U-Boot over to use them. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-13 15:56:33 +00:00
bootph-all;
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
compatible = "aspeed,ast2500-sdrammc";
reg = <0x1e6e0000 0x174
0x1e6e0200 0x1d4 >;
aspeed: Device Tree configuration for Reset Driver Add Reset Driver configuration to ast2500 SoC Device Tree and bindings for various reset signals Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:25 +00:00
#reset-cells = <1>;
clock:aspeed: Sync with Linux kernel clock header define v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-31 06:03:04 +00:00
clocks = <&scu ASPEED_CLK_MPLL>;
reset: ast2500: Use SCU for reset control The System Control Unit (SCU) controller of Aspeed SoCs provides the reset control for each peripheral. This patch refactors the reset method to leverage the SCU reset control. Thus the driver dependency on watchdog including dedicated WDT API and reset flag encoding can be eliminated. The Kconfig description is also updated accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-15 02:25:13 +00:00
resets = <&rst ASPEED_RESET_SDRAM>;
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
};
aspeed: Cleanup ast2500-u-boot.dtsi Device Tree Remove unnecessary apb and ahb nodes and just override necessary nodes/values. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:34 +00:00
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Cleanup ast2500-u-boot.dtsi Device Tree Remove unnecessary apb and ahb nodes and just override necessary nodes/values. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:34 +00:00
&uart1 {
clock:aspeed: Sync with Linux kernel clock header define v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-31 06:03:04 +00:00
clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
aspeed: Cleanup ast2500-u-boot.dtsi Device Tree Remove unnecessary apb and ahb nodes and just override necessary nodes/values. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:34 +00:00
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Cleanup ast2500-u-boot.dtsi Device Tree Remove unnecessary apb and ahb nodes and just override necessary nodes/values. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:34 +00:00
&uart2 {
clock:aspeed: Sync with Linux kernel clock header define v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-31 06:03:04 +00:00
clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
aspeed: Cleanup ast2500-u-boot.dtsi Device Tree Remove unnecessary apb and ahb nodes and just override necessary nodes/values. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:34 +00:00
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Cleanup ast2500-u-boot.dtsi Device Tree Remove unnecessary apb and ahb nodes and just override necessary nodes/values. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:34 +00:00
&uart3 {
clock:aspeed: Sync with Linux kernel clock header define v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-31 06:03:04 +00:00
clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
aspeed: Cleanup ast2500-u-boot.dtsi Device Tree Remove unnecessary apb and ahb nodes and just override necessary nodes/values. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:34 +00:00
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Cleanup ast2500-u-boot.dtsi Device Tree Remove unnecessary apb and ahb nodes and just override necessary nodes/values. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:34 +00:00
&uart4 {
clock:aspeed: Sync with Linux kernel clock header define v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-31 06:03:04 +00:00
clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
aspeed: Cleanup ast2500-u-boot.dtsi Device Tree Remove unnecessary apb and ahb nodes and just override necessary nodes/values. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:34 +00:00
};
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
aspeed: Cleanup ast2500-u-boot.dtsi Device Tree Remove unnecessary apb and ahb nodes and just override necessary nodes/values. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:34 +00:00
&uart5 {
clock:aspeed: Sync with Linux kernel clock header define v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-31 06:03:04 +00:00
clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
aspeed: Cleanup ast2500-u-boot.dtsi Device Tree Remove unnecessary apb and ahb nodes and just override necessary nodes/values. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:34 +00:00
};
&timer {
dm: dts: Convert driver model tags to use new schema Now that Linux has accepted these tags, move the device tree files in U-Boot over to use them. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-13 15:56:33 +00:00
bootph-all;
aspeed: Add basic ast2500-specific drivers and configuration Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:56 +00:00
};
aspeed: Add support for Clocks needed by MACs Add support for clocks needed by MACs to ast2500 clock driver. The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and PCLK_MAC2 for MAC1 and MAC2 respectively. The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed SDK. It is not entirely clear from the datasheet how this clock is used by MACs, so not clear if the rate would ever need to be different. So, for now, hardcoding it is probably safer. The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through hardware strapping. So, the network driver would only need to enable these clocks, no need to configure the rate. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:32 +00:00
&mac0 {
clock:aspeed: Sync with Linux kernel clock header define v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-31 06:03:04 +00:00
clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
aspeed: Add support for Clocks needed by MACs Add support for clocks needed by MACs to ast2500 clock driver. The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and PCLK_MAC2 for MAC1 and MAC2 respectively. The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed SDK. It is not entirely clear from the datasheet how this clock is used by MACs, so not clear if the rate would ever need to be different. So, for now, hardcoding it is probably safer. The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through hardware strapping. So, the network driver would only need to enable these clocks, no need to configure the rate. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:32 +00:00
};
&mac1 {
clock:aspeed: Sync with Linux kernel clock header define v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-31 06:03:04 +00:00
clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
aspeed: Add support for Clocks needed by MACs Add support for clocks needed by MACs to ast2500 clock driver. The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and PCLK_MAC2 for MAC1 and MAC2 respectively. The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed SDK. It is not entirely clear from the datasheet how this clock is used by MACs, so not clear if the rate would ever need to be different. So, for now, hardcoding it is probably safer. The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through hardware strapping. So, the network driver would only need to enable these clocks, no need to configure the rate. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:32 +00:00
};
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