2019-09-27 13:08:52 +00:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
|
|
/*
|
|
|
|
* Configuation settings for the SAM9X60EK board.
|
|
|
|
*
|
|
|
|
* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
|
|
|
|
*
|
|
|
|
* Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __CONFIG_H__
|
|
|
|
#define __CONFIG_H__
|
|
|
|
|
|
|
|
/* ARM asynchronous clock */
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_AT91_SLOW_CLOCK 32768
|
|
|
|
#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
|
2019-09-27 13:08:52 +00:00
|
|
|
|
2022-12-04 15:14:02 +00:00
|
|
|
#define CFG_USART_BASE ATMEL_BASE_DBGU
|
2022-12-04 15:14:03 +00:00
|
|
|
#define CFG_USART_ID 0 /* ignored in arm */
|
2019-09-27 13:08:52 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
|
|
|
|
* NB: in this case, USB 1.1 devices won't be recognized.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* SDRAM */
|
2022-11-16 18:10:37 +00:00
|
|
|
#define CFG_SYS_SDRAM_BASE 0x20000000
|
|
|
|
#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */
|
2019-09-27 13:08:52 +00:00
|
|
|
|
2019-09-27 13:09:07 +00:00
|
|
|
/* NAND flash */
|
|
|
|
#ifdef CONFIG_CMD_NAND
|
2022-11-12 22:36:51 +00:00
|
|
|
#define CFG_SYS_NAND_BASE 0x40000000
|
|
|
|
#define CFG_SYS_NAND_MASK_ALE BIT(21)
|
|
|
|
#define CFG_SYS_NAND_MASK_CLE BIT(22)
|
|
|
|
#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
|
|
|
|
#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5
|
2019-09-27 13:09:07 +00:00
|
|
|
#endif
|
|
|
|
|
2019-09-27 13:08:52 +00:00
|
|
|
#endif
|