u-boot/arch/riscv/include/asm/arch-andes/csr.h

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2023 Andes Technology Corporation
 */

#ifndef _ASM_ANDES_CSR_H
#define _ASM_ANDES_CSR_H

#include <asm/asm.h>
#include <linux/bitops.h>
#include <linux/const.h>

#define CSR_MCACHE_CTL 0x7ca
#define CSR_MMISC_CTL 0x7d0
#define CSR_MARCHID 0xf12
#define CSR_MCCTLCOMMAND 0x7cc

#define MCACHE_CTL_IC_EN_OFFSET 0
#define MCACHE_CTL_DC_EN_OFFSET 1
#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
#define MCACHE_CTL_DC_COHEN_OFFSET 19
#define MCACHE_CTL_DC_COHSTA_OFFSET 20

#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)
#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)
#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET)
#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)
#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)

#define CCTL_L1D_WBINVAL_ALL 6

#endif /* _ASM_ANDES_CSR_H */
riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() As the OpenSBI v1.2 does not enable the cache [0], we enable the i/d-cache in harts_early_init() and do not disable in cleanup_before_linux(). This patch also simplifies the logic and moves the CSR encoding to include/asm/arch-andes/csr.h. [0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com> 2023-02-06 08:10:47 +00:00			`// SPDX-License-Identifier: GPL-2.0+`
			`/*`
			`* Copyright (C) 2023 Andes Technology Corporation`
			`*/`

			`#ifndef _ASM_ANDES_CSR_H`
			`#define _ASM_ANDES_CSR_H`

			`#include <asm/asm.h>`
riscv: Remove common.h usage We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> 2023-10-12 23:03:59 +00:00			`#include <linux/bitops.h>`
riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() As the OpenSBI v1.2 does not enable the cache [0], we enable the i/d-cache in harts_early_init() and do not disable in cleanup_before_linux(). This patch also simplifies the logic and moves the CSR encoding to include/asm/arch-andes/csr.h. [0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com> 2023-02-06 08:10:47 +00:00			`#include <linux/const.h>`

			`#define CSR_MCACHE_CTL 0x7ca`
			`#define CSR_MMISC_CTL 0x7d0`
			`#define CSR_MARCHID 0xf12`
			`#define CSR_MCCTLCOMMAND 0x7cc`

			`#define MCACHE_CTL_IC_EN_OFFSET 0`
			`#define MCACHE_CTL_DC_EN_OFFSET 1`
			`#define MCACHE_CTL_CCTL_SUEN_OFFSET 8`
			`#define MCACHE_CTL_DC_COHEN_OFFSET 19`
			`#define MCACHE_CTL_DC_COHSTA_OFFSET 20`

			`#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)`
			`#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)`
			`#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET)`
			`#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)`
			`#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)`

			`#define CCTL_L1D_WBINVAL_ALL 6`

			`#endif /* _ASM_ANDES_CSR_H */`