2015-02-12 22:01:49 +00:00
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/*
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* (C) Copyright 2013-2015
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _MAX77620_INIT_H_
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#define _MAX77620_INIT_H_
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/* MAX77620-PMIC-specific early init regs */
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2015-07-28 22:13:17 +00:00
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#define MAX77620_I2C_ADDR 0x78
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#define MAX77620_I2C_ADDR_7BIT 0x3C
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2015-02-12 22:01:49 +00:00
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2016-07-18 19:02:11 +00:00
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#define MAX77620_CNFGGLBL1_REG 0x00
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2015-02-12 22:01:49 +00:00
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#define MAX77620_SD0_REG 0x16
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#define MAX77620_SD1_REG 0x17
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#define MAX77620_SD2_REG 0x18
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#define MAX77620_SD3_REG 0x19
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#define MAX77620_CNFG2SD_REG 0x22
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#define MAX77620_CNFG1_L0_REG 0x23
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#define MAX77620_CNFG2_L0_REG 0x24
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#define MAX77620_CNFG1_L1_REG 0x25
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#define MAX77620_CNFG2_L1_REG 0x26
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#define MAX77620_CNFG1_L2_REG 0x27
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#define MAX77620_CNFG2_L2_REG 0x28
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#define MAX77620_CNFG1_L3_REG 0x29
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#define MAX77620_CNFG2_L3_REG 0x2A
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#define MAX77620_CNFG1_L4_REG 0x2B
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#define MAX77620_CNFG2_L4_REG 0x2C
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#define MAX77620_CNFG1_L5_REG 0x2D
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#define MAX77620_CNFG2_L5_REG 0x2E
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#define MAX77620_CNFG1_L6_REG 0x2F
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#define MAX77620_CNFG2_L6_REG 0x30
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#define MAX77620_CNFG1_L7_REG 0x31
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#define MAX77620_CNFG2_L7_REG 0x32
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#define MAX77620_CNFG1_L8_REG 0x33
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#define MAX77620_CNFG2_L8_REG 0x34
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#define MAX77620_CNFG3_LDO_REG 0x35
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#define MAX77620_GPIO0_REG 0x36
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#define MAX77620_GPIO1_REG 0x37
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#define MAX77620_GPIO2_REG 0x38
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#define MAX77620_GPIO3_REG 0x39
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#define MAX77620_GPIO4_REG 0x3A
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#define MAX77620_GPIO5_REG 0x3B
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#define MAX77620_GPIO6_REG 0x3C
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#define MAX77620_GPIO7_REG 0x3D
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#define MAX77620_GPIO_PUE_GPIO 0x3E
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#define MAX77620_GPIO_PDE_GPIO 0x3F
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#define MAX77620_AME_GPIO 0x40
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#define MAX77620_REG_ONOFF_CFG1 0x41
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#define MAX77620_REG_ONOFF_CFG2 0x42
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#define MAX77620_CID0_REG 0x58
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#define MAX77620_CID1_REG 0x59
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#define MAX77620_CID2_REG 0x5A
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#define MAX77620_CID3_REG 0x5B
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#define MAX77620_CID4_REG 0x5C
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#define MAX77620_CID5_REG 0x5D
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#define I2C_SEND_2_BYTES 0x0A02
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void pmic_enable_cpu_vdd(void);
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#endif /* _MAX77620_INIT_H_ */
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