2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2012-07-05 17:21:46 +00:00
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/*
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* Copyright (C) 2012 Atmel Corporation
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*
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* Configuation settings for the AT91SAM9X5EK board.
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*/
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#ifndef __CONFIG_H__
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#define __CONFIG_H__
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/* ARM asynchronous clock */
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_AT91_SLOW_CLOCK 32768
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#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
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2012-07-05 17:21:46 +00:00
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/* general purpose I/O */
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2012-11-29 23:18:34 +00:00
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/*
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2017-05-13 02:33:27 +00:00
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* define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
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2012-11-29 23:18:34 +00:00
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* NB: in this case, USB 1.1 devices won't be recognized.
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*/
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2012-07-05 17:21:46 +00:00
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/* SDRAM */
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2022-11-16 18:10:37 +00:00
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#define CFG_SYS_SDRAM_BASE 0x20000000
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#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
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2012-07-05 17:21:46 +00:00
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/* DataFlash */
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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2022-11-12 22:36:51 +00:00
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#define CFG_SYS_NAND_BASE 0x40000000
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2012-07-05 17:21:46 +00:00
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/* our ALE is AD21 */
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2022-11-12 22:36:51 +00:00
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#define CFG_SYS_NAND_MASK_ALE (1 << 21)
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2012-07-05 17:21:46 +00:00
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/* our CLE is AD22 */
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2022-11-12 22:36:51 +00:00
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#define CFG_SYS_NAND_MASK_CLE (1 << 22)
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#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
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#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5
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2017-07-29 01:31:42 +00:00
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#endif
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2015-03-27 06:23:35 +00:00
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/* SPL */
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_MASTER_CLOCK 132096000
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#define CFG_SYS_AT91_PLLA 0x20c73f03
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#define CFG_SYS_MCKR 0x1301
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#define CFG_SYS_MCKR_CSS 0x1302
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2015-03-27 06:23:35 +00:00
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2012-07-05 17:21:46 +00:00
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#endif
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