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u-boot/board/emulation/qemu-riscv/Kconfig

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riscv: Add QEMU virt board support This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10. Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-09-26 13:55:21 +00:00
if TARGET_QEMU_VIRT
config SYS_BOARD
default "qemu-riscv"
config SYS_VENDOR
default "emulation"
config SYS_CPU
riscv: Rename cpu/qemu to cpu/generic The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-25 08:14:10 +00:00
default "generic"
riscv: Add QEMU virt board support This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10. Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-09-26 13:55:21 +00:00
config SYS_CONFIG_NAME
default "qemu-riscv"
config SYS_TEXT_BASE
riscv: qemu: add SPL configuration Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The configurations are meant to help the development of SPL on RISC-V. The configurations enable RAM as the only SPL boot device. Images must be loaded at address 0x80200000. In the default boot flow, U-Boot SPL starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is then started in supervisor mode by OpenSBI. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-21 19:14:49 +00:00
default 0x81200000 if SPL
riscv: qemu: Use different SYS_TEXT_BASE for S-mode When u-boot runs in S-mode, the M-mode runtime firmware (BBL or equivalent) uses memory range in 0x80000000 to 0x80200000. Due to this, we cannot use 0x80000000 as SYS_TEXT_BASE when running in S-mode. Instead for S-mode, we use 0x80200000 as SYS_TEXT_BASE. Even Linux RISC-V kernel ignores/reserves memory range 0x80000000 to 0x80200000 because it runs in S-mode. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-03 05:27:41 +00:00
default 0x80000000 if !RISCV_SMODE
riscv: qemu: Use correct SYS_TEXT_BASE for S-mode on 32bit system For 32bit system, the OpenSBI (or BBL) will jump to 0x80400000 address in S-mode whereas for 64bit system it will jump to 0x80200000 address in S-mode. Currently, the S-mode U-Boot sets SYS_TEXT_BASE to 0x80200000 for both 32bit and 64bit system. This breaks S-mode U-Boot for 32bit system. This patch sets different SYS_TEXT_BASE for 32bit and 64bit system so that S-mode U-Boot works fine for both. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: Karsten Merker <merker@debian.org>
2019-04-11 06:52:12 +00:00
default 0x80200000 if RISCV_SMODE && ARCH_RV64I
default 0x80400000 if RISCV_SMODE && ARCH_RV32I
riscv: Add QEMU virt board support This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10. Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-09-26 13:55:21 +00:00
riscv: qemu: add SPL configuration Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The configurations are meant to help the development of SPL on RISC-V. The configurations enable RAM as the only SPL boot device. Images must be loaded at address 0x80200000. In the default boot flow, U-Boot SPL starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is then started in supervisor mode by OpenSBI. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-21 19:14:49 +00:00
config SPL_TEXT_BASE
default 0x80000000
config SPL_OPENSBI_LOAD_ADDR
riscv: qemu: Fix kconfig build warning When 'make qemu-riscv64_defconfig', there is a build warning: board/emulation/qemu-riscv/Kconfig:24: warning: config symbol defined without type Fix it by specifying the config symbol type to 'hex'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-08-08 06:04:41 +00:00
hex
riscv: qemu: add SPL configuration Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The configurations are meant to help the development of SPL on RISC-V. The configurations enable RAM as the only SPL boot device. Images must be loaded at address 0x80200000. In the default boot flow, U-Boot SPL starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is then started in supervisor mode by OpenSBI. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-21 19:14:49 +00:00
default 0x81000000
riscv: Add QEMU virt board support This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10. Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-09-26 13:55:21 +00:00
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
riscv: Rename cpu/qemu to cpu/generic The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-25 08:14:10 +00:00
select GENERIC_RISCV
riscv: qemu: add SPL configuration Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The configurations are meant to help the development of SPL on RISC-V. The configurations enable RAM as the only SPL boot device. Images must be loaded at address 0x80200000. In the default boot flow, U-Boot SPL starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is then started in supervisor mode by OpenSBI. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-21 19:14:49 +00:00
select SUPPORT_SPL
riscv: enable SATA disk on QEMU RISC-V Allow attaching a virtual SATA disk to QEMU RISC-V by implying AHCI, AHCI_PCI, CMD_SCSI, DM_SCSI, PCI_INIT_R, SCSI, SCSI_AHCI. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-11-04 11:49:01 +00:00
imply AHCI
riscv: sort SPECIFIC_OPTIONS Sort implied options in BOARD_SPECIFIC_OPTIONS in the same sequence as in .config. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-11-04 11:49:00 +00:00
imply SMP
imply BOARD_LATE_INIT
riscv: enable SATA disk on QEMU RISC-V Allow attaching a virtual SATA disk to QEMU RISC-V by implying AHCI, AHCI_PCI, CMD_SCSI, DM_SCSI, PCI_INIT_R, SCSI, SCSI_AHCI. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-11-04 11:49:01 +00:00
imply PCI_INIT_R
riscv: sort SPECIFIC_OPTIONS Sort implied options in BOARD_SPECIFIC_OPTIONS in the same sequence as in .config. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-11-04 11:49:00 +00:00
imply SPL_RAM_SUPPORT
imply SPL_RAM_DEVICE
imply CMD_PCI
imply CMD_POWEROFF
riscv: enable SATA disk on QEMU RISC-V Allow attaching a virtual SATA disk to QEMU RISC-V by implying AHCI, AHCI_PCI, CMD_SCSI, DM_SCSI, PCI_INIT_R, SCSI, SCSI_AHCI. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-11-04 11:49:01 +00:00
imply CMD_SCSI
riscv: qemu: Include some useful commands With the virtio net and blk drivers, we can do more stuff with some useful commands. Imply those in the board Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-15 09:21:14 +00:00
imply CMD_PING
imply CMD_EXT2
imply CMD_EXT4
imply CMD_FAT
riscv: sort SPECIFIC_OPTIONS Sort implied options in BOARD_SPECIFIC_OPTIONS in the same sequence as in .config. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-11-04 11:49:00 +00:00
imply CMD_FS_GENERIC
imply DOS_PARTITION
imply ISO_PARTITION
imply EFI_PARTITION
riscv: enable SATA disk on QEMU RISC-V Allow attaching a virtual SATA disk to QEMU RISC-V by implying AHCI, AHCI_PCI, CMD_SCSI, DM_SCSI, PCI_INIT_R, SCSI, SCSI_AHCI. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-11-04 11:49:01 +00:00
imply SCSI_AHCI
imply AHCI_PCI
riscv: sort SPECIFIC_OPTIONS Sort implied options in BOARD_SPECIFIC_OPTIONS in the same sequence as in .config. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-11-04 11:49:00 +00:00
imply E1000
imply NVME
riscv: qemu: Enable PCI host ECAM generic driver QEMU 4.0.0 'virt' target integrates a generic ECAM PCI host. Enable the driver for it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-05-15 15:42:58 +00:00
imply PCI
imply PCIE_ECAM_GENERIC
riscv: enable SATA disk on QEMU RISC-V Allow attaching a virtual SATA disk to QEMU RISC-V by implying AHCI, AHCI_PCI, CMD_SCSI, DM_SCSI, PCI_INIT_R, SCSI, SCSI_AHCI. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-11-04 11:49:01 +00:00
imply SCSI
imply DM_SCSI
riscv: sort SPECIFIC_OPTIONS Sort implied options in BOARD_SPECIFIC_OPTIONS in the same sequence as in .config. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-11-04 11:49:00 +00:00
imply SYS_NS16550
imply SIFIVE_SERIAL
riscv: qemu: Enable HTIF console support Enable support for HTIF console so that we can use QEMU RISC-V U-Boot on RISC-V emulators and ISS having it. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2022-01-27 06:11:08 +00:00
imply HTIF_CONSOLE if 64BIT
riscv: qemu: Add syscon reboot and poweroff support This adds syscon reboot and poweroff support to QEMU RISC-V. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-06-23 05:29:45 +00:00
imply SYSRESET
imply SYSRESET_CMD_POWEROFF
riscv: sort SPECIFIC_OPTIONS Sort implied options in BOARD_SPECIFIC_OPTIONS in the same sequence as in .config. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-11-04 11:49:00 +00:00
imply SYSRESET_SYSCON
imply VIRTIO_MMIO
imply VIRTIO_PCI
imply VIRTIO_NET
imply VIRTIO_BLK
riscv: qemu: Enable MTD NOR flash support Enable support to the 2 NOR flashes on the QEMU RISC-V virt machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2021-08-07 05:00:02 +00:00
imply MTD_NOR_FLASH
imply CFI_FLASH
fdt: Enable OF_HAS_PRIOR_STAGE for most boards with OF_BOARD Use this new Kconfig instead of OF_BOARD, so we know for sure which boards obtain their devicetree from a prior stage. Leave sandbox alone since it does not. Also don't touch xilinx_versal_virt since it does not have a specific TARGET Kconfig. This option implies OF_BOARD for now, but with future work standard passage may be used instead. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add rpi_4_32b and rpi_arm64 to the list of boards converted] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-17 03:59:36 +00:00
imply OF_HAS_PRIOR_STAGE
riscv: Add QEMU virt board support This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10. Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-09-26 13:55:21 +00:00
endif
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