2010-09-11 07:31:43 +00:00
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/*
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* (C) Copyright 2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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2013-10-07 11:07:26 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2010-09-11 07:31:43 +00:00
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*/
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#ifndef _PPC460SX_H_
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#define _PPC460SX_H_
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#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
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2010-09-20 14:05:31 +00:00
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/* Memory mapped registers */
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#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* Internal Peripherals */
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
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#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
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2010-09-11 07:31:43 +00:00
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#define SDR0_SRST0_DMC 0x00200000
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#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
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#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
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#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
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#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
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#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */
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#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
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#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
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#endif /* _PPC460SX_H_ */
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