mirror of
https://github.com/AsahiLinux/u-boot
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72 lines
2.1 KiB
ArmAsm
72 lines
2.1 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2021 Nuvoton Technology Corp.
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*/
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.align 5
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#include <linux/linkage.h>
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#ifndef CONFIG_SYS_L2CACHE_OFF
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ENTRY(l2_pl310_init)
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@------------------------------------------------------------------
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@ L2CC (PL310) Initialization
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@------------------------------------------------------------------
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@ In this example PL310 PA = VA. The memory was marked as Device memory
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@ in previous stages when defining CORE0 private address space
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LDR r0, =0xF03FC000 @ A9_BASE_ADDR
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@ Disable L2 Cache controller just in case it is already on
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LDR r1, =0x0
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STR r1, [r0,#0x100]
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@ Set aux cntrl
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@ Way size = 32KB
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@ Way = 16
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LDR r1, =0x02050000
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ORR r1, r1, #(1 << 29) @ Instruction prefetch enable
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ORR r1, r1, #(1 << 28) @ Data prefetch enable
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ORR r1, r1, #(1 << 22) @ cache replacement policy
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STR r1, [r0,#0x104] @ auxilary control reg at offset 0x104
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@ Set tag RAM latency
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@ 1 cycle RAM write access latency
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@ 1 cycle RAM read access latency
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@ 1 cycle RAM setup latency
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LDR r1, =0x00000000
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STR r1, [r0,#0x108] @ tag ram control reg at offset 0x108
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@ Set Data RAM latency
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@ 1 cycle RAM write access latency
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@ 2 cycles RAM read access latency
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@ 1 cycle RAM setup latency
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LDR r1, =0x00000000
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STR r1, [r0,#0x10C] @ data ram control reg at offset 0x108
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@Cache maintenance - invalidate 16 ways (0xffff) - base offset 0x77C
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LDR r1, =0xFFFF
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STR r1, [r0,#0x77C] @ invalidate by way register at offset 0x77C
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poll_invalidate:
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LDR r1, [r0,#0x77C] @ invalidate by way register at offset 0x77C
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TST r1, #1
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BNE poll_invalidate
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@ Ensure L2 remains disabled for the time being
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LDR r1, =0x0
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STR r1, [r0,#0x100]
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MRC p15, 4, r0, c15, c0, 0 @ Read periph base address
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@ SCU offset from base of private peripheral space = 0x000
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LDR r1, [r0, #0x0] @ Read the SCU Control Register
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ORR r1, r1, #0x1 @ Set bit 0 (The Enable bit)
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STR r1, [r0, #0x0] @ Write back modifed value
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BX lr
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ENDPROC(l2_pl310_init)
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#endif
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