u-boot/arch/x86/cpu/broadwell/Makefile

#
# Copyright (c) 2016 Google, Inc
#
# SPDX-License-Identifier:	GPL-2.0+
#

obj-y += cpu.o
obj-y += iobp.o
obj-y += lpc.o
obj-y += me.o
obj-y += northbridge.o
obj-y += pch.o
obj-y += pinctrl_broadwell.o
obj-y += power_state.o
obj-y += refcode.o
obj-y += sata.o
obj-y += sdram.o
x86: Add basic support for broadwell This adds the broadwell architecture, with the CPU driver and some useful header files. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:07:18 +00:00			`#`
			`# Copyright (c) 2016 Google, Inc`
			`#`
			`# SPDX-License-Identifier: GPL-2.0+`
			`#`

			`obj-y += cpu.o`
x86: broadwell: Add a PCH driver Add a driver for the broadwell low-power platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:07:19 +00:00			`obj-y += iobp.o`
x86: broadwell: Add an LPC driver Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly uses common code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:07:23 +00:00			`obj-y += lpc.o`
x86: broadwell: Add support for high-speed I/O lane with ME Provide a way to determine the HSIO (high-speed I/O) version supported by the Intel Management Engine (ME) implementation on the platform. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:07:28 +00:00			`obj-y += me.o`
x86: broadwell: Add a northbridge driver Add a driver for the broadwell northbridge. This sets up the location of several blocks of registers. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:07:22 +00:00			`obj-y += northbridge.o`
x86: broadwell: Add a PCH driver Add a driver for the broadwell low-power platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:07:19 +00:00			`obj-y += pch.o`
x86: broadwell: Add a pinctrl driver GPIO pins need to be set up on start-up. Add a driver to provide this, configured from the device tree. The binding is slightly different from the existing ICH6 binding, since that is quite verbose. The new binding should be just as extensible. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:07:20 +00:00			`obj-y += pinctrl_broadwell.o`
x86: broadwell: Add power-control support Broadwell requires quite a bit of power-management setup. Add code to set this up correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598373/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:07:25 +00:00			`obj-y += power_state.o`
x86: broadwell: Add reference code support Broadwell needs a special binary blob to set up the PCH. Add code to run this on start-up. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:07:24 +00:00			`obj-y += refcode.o`
x86: broadwell: Add a SATA driver Add a SATA driver for broadwell. This supports connecting an SSD and the usual U-Boot commands to read and write data. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:07:21 +00:00			`obj-y += sata.o`
x86: broadwell: Add support for SDRAM setup Broadwell uses a binary blob called the memory reference code (MRC) to start up its SDRAM. This is similar to ivybridge so we can mostly use common code for running this blob. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> 2016-03-12 05:07:26 +00:00			`obj-y += sdram.o`