u-boot/arch/blackfin/include/asm/cplb.h

/*
 * cplb.h - defines for managing CPLB tables
 *
 * Copyright (c) 2002-2007 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#ifndef __ASM_BLACKFIN_CPLB_H__
#define __ASM_BLACKFIN_CPLB_H__

#include <asm/mach-common/bits/mpu.h>

#define CPLB_ENABLE_ICACHE_P	0
#define CPLB_ENABLE_DCACHE_P	1
#define CPLB_ENABLE_DCACHE2_P	2
#define CPLB_ENABLE_CPLBS_P	3	/* Deprecated! */
#define CPLB_ENABLE_ICPLBS_P	4
#define CPLB_ENABLE_DCPLBS_P	5

#define CPLB_ENABLE_ICACHE	(1<<CPLB_ENABLE_ICACHE_P)
#define CPLB_ENABLE_DCACHE	(1<<CPLB_ENABLE_DCACHE_P)
#define CPLB_ENABLE_DCACHE2	(1<<CPLB_ENABLE_DCACHE2_P)
#define CPLB_ENABLE_CPLBS	(1<<CPLB_ENABLE_CPLBS_P)
#define CPLB_ENABLE_ICPLBS	(1<<CPLB_ENABLE_ICPLBS_P)
#define CPLB_ENABLE_DCPLBS	(1<<CPLB_ENABLE_DCPLBS_P)
#define CPLB_ENABLE_ANY_CPLBS	CPLB_ENABLE_CPLBS | \
				CPLB_ENABLE_ICPLBS | \
				CPLB_ENABLE_DCPLBS

#define CPLB_RELOADED		0x0000
#define CPLB_NO_UNLOCKED	0x0001
#define CPLB_NO_ADDR_MATCH	0x0002
#define CPLB_PROT_VIOL		0x0003

#define CPLB_DEF_CACHE		CPLB_L1_CHBL | CPLB_WT
#define CPLB_CACHE_ENABLED	CPLB_L1_CHBL | CPLB_DIRTY

#define CPLB_ALL_ACCESS	CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR

#define CPLB_I_PAGE_MGMT	CPLB_LOCK | CPLB_VALID
#define CPLB_D_PAGE_MGMT	CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
#define CPLB_DNOCACHE		CPLB_ALL_ACCESS | CPLB_VALID
#define CPLB_DDOCACHE		CPLB_DNOCACHE | CPLB_DEF_CACHE
#define CPLB_INOCACHE		CPLB_USER_RD | CPLB_VALID
#define CPLB_IDOCACHE		CPLB_INOCACHE | CPLB_L1_CHBL

/* Data Attibutes*/
#if defined(__ADSPBF60x__)
#define SDRAM_IGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | \
				CPLB_USER_RD | CPLB_VALID)
#else
#define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | \
				CPLB_USER_RD | CPLB_VALID)
#endif
#define SDRAM_IKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define L1_IMEMORY              (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define SDRAM_INON_CHBL         (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)

#if ANOMALY_05000158
# define ANOMALY_05000158_WORKAROUND 0x200
#else
# define ANOMALY_05000158_WORKAROUND 0
#endif

#ifdef CONFIG_DCACHE_WB		/*Write Back Policy */
#if defined(__ADSPBF60x__)
#define SDRAM_DGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | \
				CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
				CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#else
#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | \
				CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
				CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#endif
#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
#define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)

#else				/*Write Through */
#if defined(__ADSPBF60x__)
#define SDRAM_DGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_WT | \
				CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
				CPLB_USER_WR | CPLB_VALID | \
				ANOMALY_05000158_WORKAROUND)
#else
#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | \
				CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
				CPLB_USER_WR | CPLB_VALID | \
				ANOMALY_05000158_WORKAROUND)
#endif
#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
#define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#endif

#endif				/* _CPLB_H */
punt Blackfin VDSP headers and import sanitized/auto-generated ones Signed-off-by: Mike Frysinger <vapier@gentoo.org> 2008-02-05 00:26:55 +00:00			`/*`
			`* cplb.h - defines for managing CPLB tables`
Add missing Blackfin files. 2006-03-12 01:12:27 +00:00			`*`
punt Blackfin VDSP headers and import sanitized/auto-generated ones Signed-off-by: Mike Frysinger <vapier@gentoo.org> 2008-02-05 00:26:55 +00:00			`* Copyright (c) 2002-2007 Analog Devices Inc.`
Add missing Blackfin files. 2006-03-12 01:12:27 +00:00			`*`
punt Blackfin VDSP headers and import sanitized/auto-generated ones Signed-off-by: Mike Frysinger <vapier@gentoo.org> 2008-02-05 00:26:55 +00:00			`* Licensed under the GPL-2 or later.`
			`*/`
Add missing Blackfin files. 2006-03-12 01:12:27 +00:00
punt Blackfin VDSP headers and import sanitized/auto-generated ones Signed-off-by: Mike Frysinger <vapier@gentoo.org> 2008-02-05 00:26:55 +00:00			`#ifndef __ASM_BLACKFIN_CPLB_H__`
			`#define __ASM_BLACKFIN_CPLB_H__`
Add missing Blackfin files. 2006-03-12 01:12:27 +00:00
punt Blackfin VDSP headers and import sanitized/auto-generated ones Signed-off-by: Mike Frysinger <vapier@gentoo.org> 2008-02-05 00:26:55 +00:00			`#include <asm/mach-common/bits/mpu.h>`
[Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support 2007-03-09 05:38:44 +00:00
Add missing Blackfin files. 2006-03-12 01:12:27 +00:00			`#define CPLB_ENABLE_ICACHE_P 0`
			`#define CPLB_ENABLE_DCACHE_P 1`
			`#define CPLB_ENABLE_DCACHE2_P 2`
[Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support 2007-03-09 05:38:44 +00:00			`#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */`
Add missing Blackfin files. 2006-03-12 01:12:27 +00:00			`#define CPLB_ENABLE_ICPLBS_P 4`
			`#define CPLB_ENABLE_DCPLBS_P 5`

			`#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)`
			`#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)`
			`#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)`
			`#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)`
			`#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)`
			`#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)`
			`#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS \| \`
			`CPLB_ENABLE_ICPLBS \| \`
			`CPLB_ENABLE_DCPLBS`

			`#define CPLB_RELOADED 0x0000`
			`#define CPLB_NO_UNLOCKED 0x0001`
			`#define CPLB_NO_ADDR_MATCH 0x0002`
			`#define CPLB_PROT_VIOL 0x0003`

			`#define CPLB_DEF_CACHE CPLB_L1_CHBL \| CPLB_WT`
			`#define CPLB_CACHE_ENABLED CPLB_L1_CHBL \| CPLB_DIRTY`

			`#define CPLB_ALL_ACCESS CPLB_SUPV_WR \| CPLB_USER_RD \| CPLB_USER_WR`

			`#define CPLB_I_PAGE_MGMT CPLB_LOCK \| CPLB_VALID`
			`#define CPLB_D_PAGE_MGMT CPLB_LOCK \| CPLB_ALL_ACCESS \| CPLB_VALID`
			`#define CPLB_DNOCACHE CPLB_ALL_ACCESS \| CPLB_VALID`
			`#define CPLB_DDOCACHE CPLB_DNOCACHE \| CPLB_DEF_CACHE`
Big white-space cleanup. This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de> 2008-05-20 14:00:29 +00:00			`#define CPLB_INOCACHE CPLB_USER_RD \| CPLB_VALID`
			`#define CPLB_IDOCACHE CPLB_INOCACHE \| CPLB_L1_CHBL`
Add missing Blackfin files. 2006-03-12 01:12:27 +00:00
[Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support 2007-03-09 05:38:44 +00:00			`/* Data Attibutes*/`
blackfin: bf60x: support big cplb page BF60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for them. So that bf609-ezkit can use it's 128M memory. Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com> 2011-10-25 10:07:58 +00:00			`#if defined(__ADSPBF60x__)`
			`#define SDRAM_IGENERIC (PAGE_SIZE_16MB \| CPLB_L1_CHBL \| \`
			`CPLB_USER_RD \| CPLB_VALID)`
			`#else`
			`#define SDRAM_IGENERIC (PAGE_SIZE_4MB \| CPLB_L1_CHBL \| \`
			`CPLB_USER_RD \| CPLB_VALID)`
			`#endif`
[Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support 2007-03-09 05:38:44 +00:00			`#define SDRAM_IKERNEL (PAGE_SIZE_4MB \| CPLB_L1_CHBL \| CPLB_USER_RD \| CPLB_VALID \| CPLB_LOCK)`
[Blackfin][PATCH] Fix dynamic CPLB generation issue 2007-04-05 10:33:04 +00:00			`#define L1_IMEMORY (PAGE_SIZE_1MB \| CPLB_USER_RD \| CPLB_VALID \| CPLB_LOCK)`
[Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support 2007-03-09 05:38:44 +00:00			`#define SDRAM_INON_CHBL (PAGE_SIZE_4MB \| CPLB_USER_RD \| CPLB_VALID)`

punt Blackfin VDSP headers and import sanitized/auto-generated ones Signed-off-by: Mike Frysinger <vapier@gentoo.org> 2008-02-05 00:26:55 +00:00			`#if ANOMALY_05000158`
			`# define ANOMALY_05000158_WORKAROUND 0x200`
			`#else`
			`# define ANOMALY_05000158_WORKAROUND 0`
			`#endif`
[Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support 2007-03-09 05:38:44 +00:00
punt Blackfin VDSP headers and import sanitized/auto-generated ones Signed-off-by: Mike Frysinger <vapier@gentoo.org> 2008-02-05 00:26:55 +00:00			`#ifdef CONFIG_DCACHE_WB /Write Back Policy /`
blackfin: bf60x: support big cplb page BF60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for them. So that bf609-ezkit can use it's 128M memory. Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com> 2011-10-25 10:07:58 +00:00			`#if defined(__ADSPBF60x__)`
			`#define SDRAM_DGENERIC (PAGE_SIZE_16MB \| CPLB_L1_CHBL \| CPLB_DIRTY \| \`
			`CPLB_SUPV_WR \| CPLB_USER_WR \| CPLB_USER_RD \| \`
			`CPLB_VALID \| ANOMALY_05000158_WORKAROUND)`
			`#else`
			`#define SDRAM_DGENERIC (PAGE_SIZE_4MB \| CPLB_L1_CHBL \| CPLB_DIRTY \| \`
			`CPLB_SUPV_WR \| CPLB_USER_WR \| CPLB_USER_RD \| \`
			`CPLB_VALID \| ANOMALY_05000158_WORKAROUND)`
			`#endif`
punt Blackfin VDSP headers and import sanitized/auto-generated ones Signed-off-by: Mike Frysinger <vapier@gentoo.org> 2008-02-05 00:26:55 +00:00			`#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB \| CPLB_DIRTY \| CPLB_SUPV_WR \| CPLB_USER_RD \| CPLB_USER_WR \| CPLB_VALID \| ANOMALY_05000158_WORKAROUND)`
			`#define SDRAM_DKERNEL (PAGE_SIZE_4MB \| CPLB_L1_CHBL \| CPLB_USER_RD \| CPLB_USER_WR \| CPLB_DIRTY \| CPLB_SUPV_WR \| CPLB_VALID \| CPLB_LOCK \| ANOMALY_05000158_WORKAROUND)`
			`#define L1_DMEMORY (PAGE_SIZE_4MB \| CPLB_SUPV_WR \| CPLB_USER_WR \| CPLB_USER_RD \| CPLB_VALID \| ANOMALY_05000158_WORKAROUND)`
			`#define SDRAM_EBIU (PAGE_SIZE_4MB \| CPLB_DIRTY \| CPLB_USER_RD \| CPLB_USER_WR \| CPLB_SUPV_WR \| CPLB_VALID \| ANOMALY_05000158_WORKAROUND)`
[Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support 2007-03-09 05:38:44 +00:00
			`#else /Write Through /`
blackfin: bf60x: support big cplb page BF60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for them. So that bf609-ezkit can use it's 128M memory. Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com> 2011-10-25 10:07:58 +00:00			`#if defined(__ADSPBF60x__)`
			`#define SDRAM_DGENERIC (PAGE_SIZE_16MB \| CPLB_L1_CHBL \| CPLB_WT \| \`
			`CPLB_L1_AOW \| CPLB_SUPV_WR \| CPLB_USER_RD \| \`
			`CPLB_USER_WR \| CPLB_VALID \| \`
			`ANOMALY_05000158_WORKAROUND)`
			`#else`
			`#define SDRAM_DGENERIC (PAGE_SIZE_4MB \| CPLB_L1_CHBL \| CPLB_WT \| \`
			`CPLB_L1_AOW \| CPLB_SUPV_WR \| CPLB_USER_RD \| \`
			`CPLB_USER_WR \| CPLB_VALID \| \`
			`ANOMALY_05000158_WORKAROUND)`
			`#endif`
punt Blackfin VDSP headers and import sanitized/auto-generated ones Signed-off-by: Mike Frysinger <vapier@gentoo.org> 2008-02-05 00:26:55 +00:00			`#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB \| CPLB_WT \| CPLB_L1_AOW \| CPLB_SUPV_WR \| CPLB_USER_WR \| CPLB_USER_RD \| CPLB_VALID \| ANOMALY_05000158_WORKAROUND)`
			`#define SDRAM_DKERNEL (PAGE_SIZE_4MB \| CPLB_L1_CHBL \| CPLB_WT \| CPLB_L1_AOW \| CPLB_USER_RD \| CPLB_SUPV_WR \| CPLB_USER_WR \| CPLB_VALID \| CPLB_LOCK \| ANOMALY_05000158_WORKAROUND)`
			`#define L1_DMEMORY (PAGE_SIZE_4MB \| CPLB_SUPV_WR \| CPLB_USER_WR \| CPLB_VALID \| ANOMALY_05000158_WORKAROUND)`
			`#define SDRAM_EBIU (PAGE_SIZE_4MB \| CPLB_WT \| CPLB_L1_AOW \| CPLB_USER_RD \| CPLB_USER_WR \| CPLB_SUPV_WR \| CPLB_VALID \| ANOMALY_05000158_WORKAROUND)`
[Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support 2007-03-09 05:38:44 +00:00			`#endif`

			`#endif /* _CPLB_H */`