mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
[Blackfin][PATCH] Fix dynamic CPLB generation issue
This commit is contained in:
Aubrey Li
parent
0445e3a264
commit
7b7e30aa64
5 changed files with 23 additions and 906 deletions
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@ -93,7 +93,7 @@ void icache_enable(void)
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/* Fill the rest with invalid entry */
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if (j <= 15) {
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for (; j <= 16; j++) {
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for (; j < 16; j++) {
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debug("filling %i with 0", j);
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*I1++ = 0x0;
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}
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@ -169,7 +169,7 @@ void dcache_enable(void)
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/* Fill the rest with invalid entry */
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if (j <= 15) {
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for (; j <= 16; j++) {
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for (; j < 16; j++) {
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debug("filling %i with 0", j);
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*I1++ = 0x0;
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}
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@ -1,482 +0,0 @@
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/*This file is subject to the terms and conditions of the GNU General Public
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* License.
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*
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* Blackfin BF533/2.6 support : LG Soft India
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* Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
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* Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
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* shouldn't be victimized. cplbmgr.S search logic is corrected
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* to findout the appropriate victim.
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* 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
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* : LG Soft India
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*/
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#include <config.h>
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#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
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#define __ARCH_BFINNOMMU_CPLBTAB_H
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/*************************************************************************
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* ICPLB TABLE
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*************************************************************************/
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.data
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/* This table is configurable */
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.align 4;
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/* Data Attibutes*/
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#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
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#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
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#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
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#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
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/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
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#define ANOMALY_05000158 0x200
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#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
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#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
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#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
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#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
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#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
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#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
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#else /*Write Through */
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#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
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#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
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#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
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#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
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#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
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#endif
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.align 4;
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.global _ipdt_table _ipdt_table:.byte4 0x00000000;
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.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */
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.byte4 0x00400000;
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.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */
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.byte4 0x00800000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */
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.byte4 0x00C00000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */
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.byte4 0x01000000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */
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.byte4 0x01400000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */
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.byte4 0x01800000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */
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.byte4 0x01C00000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */
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#ifndef CONFIG_EZKIT /*STAMP Memory regions */
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.byte4 0x02000000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */
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.byte4 0x02400000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */
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.byte4 0x02800000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */
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.byte4 0x02C00000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */
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.byte4 0x03000000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */
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.byte4 0x03400000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */
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.byte4 0x03800000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */
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.byte4 0x03C00000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */
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#endif
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.byte4 0x20000000;
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.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */
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#ifdef CONFIG_STAMP
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.byte4 0x04000000;
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.byte4(SDRAM_IGENERIC);
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.byte4 0x04400000;
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.byte4(SDRAM_IGENERIC);
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.byte4 0x04800000;
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.byte4(SDRAM_IGENERIC);
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.byte4 0x04C00000;
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.byte4(SDRAM_IGENERIC);
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.byte4 0x05000000;
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.byte4(SDRAM_IGENERIC);
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.byte4 0x05400000;
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.byte4(SDRAM_IGENERIC);
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.byte4 0x05800000;
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.byte4(SDRAM_IGENERIC);
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.byte4 0x05C00000;
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.byte4(SDRAM_IGENERIC);
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.byte4 0x06000000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page25 */
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.byte4 0x06400000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page26 */
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.byte4 0x06800000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page27 */
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.byte4 0x06C00000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page28 */
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.byte4 0x07000000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page29 */
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.byte4 0x07400000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page30 */
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.byte4 0x07800000;
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.byte4(SDRAM_IGENERIC); /*SDRAM_Page31 */
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.byte4 0x07C00000;
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.byte4(SDRAM_IKERNEL); /*SDRAM_Page32 */
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#endif
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.byte4 0xffffffff; /* end of section - termination */
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/**********************************************************************
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* PAGE DESCRIPTOR TABLE
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*
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**********************************************************************/
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/* Till here we are discussing about the static memory management model.
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* However, the operating envoronments commonly define more CPLB
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* descriptors to cover the entire addressable memory than will fit into
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* the available on-chip 16 CPLB MMRs. When this happens, the below table
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* will be used which will hold all the potentially required CPLB descriptors
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*
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* This is how Page descriptor Table is implemented in uClinux/Blackfin.
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*/
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.global _dpdt_table _dpdt_table:.byte4 0x00000000;
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.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */
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.byte4 0x00400000;
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.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */
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.byte4 0x00800000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */
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.byte4 0x00C00000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */
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.byte4 0x01000000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */
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.byte4 0x01400000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */
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.byte4 0x01800000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */
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.byte4 0x01C00000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */
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#ifndef CONFIG_EZKIT
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.byte4 0x02000000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */
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.byte4 0x02400000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */
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.byte4 0x02800000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */
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.byte4 0x02C00000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */
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.byte4 0x03000000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */
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.byte4 0x03400000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */
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.byte4 0x03800000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */
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.byte4 0x03C00000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */
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#endif
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#ifdef CONFIG_STAMP
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.byte4 0x04000000;
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.byte4(SDRAM_DGENERIC);
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.byte4 0x04400000;
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.byte4(SDRAM_DGENERIC);
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.byte4 0x04800000;
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.byte4(SDRAM_DGENERIC);
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.byte4 0x04C00000;
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.byte4(SDRAM_DGENERIC);
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.byte4 0x05000000;
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.byte4(SDRAM_DGENERIC);
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.byte4 0x05400000;
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.byte4(SDRAM_DGENERIC);
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.byte4 0x05800000;
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.byte4(SDRAM_DGENERIC);
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.byte4 0x05C00000;
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.byte4(SDRAM_DGENERIC);
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.byte4 0x06000000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page25 */
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.byte4 0x06400000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page26 */
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.byte4 0x06800000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page27 */
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.byte4 0x06C00000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page28 */
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.byte4 0x07000000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page29 */
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.byte4 0x07400000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page30 */
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.byte4 0x07800000;
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.byte4(SDRAM_DGENERIC); /*SDRAM_Page31 */
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.byte4 0x07C00000;
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.byte4(SDRAM_DKERNEL); /*SDRAM_Page32 */
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#endif
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.byte4 0x20000000;
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.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */
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#if (BFIN_CPU == ADSP_BF533)
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.byte4 0xFF800000;
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.byte4(L1_DMEMORY);
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.byte4 0xFF801000;
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.byte4(L1_DMEMORY);
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.byte4 0xFF802000;
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.byte4(L1_DMEMORY);
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.byte4 0xFF803000;
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.byte4(L1_DMEMORY);
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#endif
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.byte4 0xFF804000;
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.byte4(L1_DMEMORY);
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.byte4 0xFF805000;
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.byte4(L1_DMEMORY);
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.byte4 0xFF806000;
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.byte4(L1_DMEMORY);
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.byte4 0xFF807000;
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.byte4(L1_DMEMORY);
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#if (BFIN_CPU == ADSP_BF533)
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.byte4 0xFF900000;
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.byte4(L1_DMEMORY);
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.byte4 0xFF901000;
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.byte4(L1_DMEMORY);
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.byte4 0xFF902000;
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.byte4(L1_DMEMORY);
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.byte4 0xFF903000;
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.byte4(L1_DMEMORY);
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#endif
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#if ((BFIN_CPU == ADSP_BF532) || (BFIN_CPU == ADSP_BF533))
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.byte4 0xFF904000;
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.byte4(L1_DMEMORY);
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.byte4 0xFF905000;
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.byte4(L1_DMEMORY);
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.byte4 0xFF906000;
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.byte4(L1_DMEMORY);
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.byte4 0xFF907000;
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.byte4(L1_DMEMORY);
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#endif
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.byte4 0xFFB00000;
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.byte4(L1_DMEMORY);
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.byte4 0xffffffff; /*end of section - termination */
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#ifdef CONFIG_CPLB_INFO
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.global _ipdt_swapcount_table; /* swapin count first, then swapout count */
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_ipdt_swapcount_table:
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000; /* 10 */
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000; /* 20 */
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000; /* 30 */
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000; /* 40 */
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000; /* 50 */
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000; /* 60 */
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000; /* 70 */
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000; /* 80 */
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000; /* 90 */
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000; /* 100 */
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.global _dpdt_swapcount_table; /* swapin count first, then swapout count */
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_dpdt_swapcount_table:
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000; /* 10 */
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000;
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.byte4 0x00000000; /* 20 */
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.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 30 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 40 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 50 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 60 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 70 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 80 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 80 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 100 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 110 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 120 */
|
||||
#endif
|
||||
|
||||
#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/
|
||||
|
|
@ -1,408 +0,0 @@
|
|||
/*This file is subject to the terms and conditions of the GNU General Public
|
||||
* License.
|
||||
*
|
||||
* Blackfin BF533/2.6 support : LG Soft India
|
||||
* Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
|
||||
* Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
|
||||
* shouldn't be victimized. cplbmgr.S search logic is corrected
|
||||
* to findout the appropriate victim.
|
||||
* 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
|
||||
* : LG Soft India
|
||||
*/
|
||||
#include <config.h>
|
||||
|
||||
#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
|
||||
#define __ARCH_BFINNOMMU_CPLBTAB_H
|
||||
|
||||
/*
|
||||
* ICPLB TABLE
|
||||
*/
|
||||
|
||||
.data
|
||||
/* This table is configurable */
|
||||
.align 4;
|
||||
|
||||
/* Data Attibutes*/
|
||||
|
||||
#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
|
||||
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
|
||||
|
||||
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
|
||||
|
||||
#define ANOMALY_05000158 0x200
|
||||
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
|
||||
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
|
||||
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
|
||||
#else /*Write Through */
|
||||
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
|
||||
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
#endif
|
||||
|
||||
.align 4;
|
||||
.global _ipdt_table _ipdt_table:.byte4 0x00000000;
|
||||
.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */
|
||||
.byte4 0x00400000;
|
||||
.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */
|
||||
.byte4 0x00800000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */
|
||||
.byte4 0x00C00000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */
|
||||
.byte4 0x01000000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */
|
||||
.byte4 0x01400000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */
|
||||
.byte4 0x01800000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */
|
||||
.byte4 0x01C00000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */
|
||||
.byte4 0x02000000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */
|
||||
.byte4 0x02400000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */
|
||||
.byte4 0x02800000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */
|
||||
.byte4 0x02C00000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */
|
||||
.byte4 0x03000000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */
|
||||
.byte4 0x03400000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */
|
||||
.byte4 0x03800000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */
|
||||
.byte4 0x03C00000;
|
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */
|
||||
.byte4 0x20000000;
|
||||
.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */
|
||||
|
||||
.byte4 0xffffffff; /* end of section - termination */
|
||||
|
||||
/*
|
||||
* PAGE DESCRIPTOR TABLE
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Till here we are discussing about the static memory management model.
|
||||
* However, the operating envoronments commonly define more CPLB
|
||||
* descriptors to cover the entire addressable memory than will fit into
|
||||
* the available on-chip 16 CPLB MMRs. When this happens, the below table
|
||||
* will be used which will hold all the potentially required CPLB descriptors
|
||||
*
|
||||
* This is how Page descriptor Table is implemented in uClinux/Blackfin.
|
||||
*/
|
||||
.global _dpdt_table _dpdt_table:.byte4 0x00000000;
|
||||
.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */
|
||||
.byte4 0x00400000;
|
||||
.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */
|
||||
.byte4 0x00800000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */
|
||||
.byte4 0x00C00000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */
|
||||
.byte4 0x01000000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */
|
||||
.byte4 0x01400000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */
|
||||
.byte4 0x01800000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */
|
||||
.byte4 0x01C00000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */
|
||||
.byte4 0x02000000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */
|
||||
.byte4 0x02400000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */
|
||||
.byte4 0x02800000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */
|
||||
.byte4 0x02C00000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */
|
||||
.byte4 0x03000000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */
|
||||
.byte4 0x03400000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */
|
||||
.byte4 0x03800000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */
|
||||
.byte4 0x03C00000;
|
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */
|
||||
.byte4 0x20000000;
|
||||
.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */
|
||||
|
||||
#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537))
|
||||
.byte4 0xFF800000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF801000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF802000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF803000;
|
||||
.byte4(L1_DMEMORY);
|
||||
#endif
|
||||
.byte4 0xFF804000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF805000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF806000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF807000;
|
||||
.byte4(L1_DMEMORY);
|
||||
#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537))
|
||||
.byte4 0xFF900000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF901000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF902000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF903000;
|
||||
.byte4(L1_DMEMORY);
|
||||
#endif
|
||||
.byte4 0xFF904000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF905000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF906000;
|
||||
.byte4(L1_DMEMORY);
|
||||
.byte4 0xFF907000;
|
||||
.byte4(L1_DMEMORY);
|
||||
|
||||
.byte4 0xFFB00000;
|
||||
.byte4(L1_DMEMORY);
|
||||
|
||||
.byte4 0xffffffff; /*end of section - termination */
|
||||
|
||||
#ifdef CONFIG_CPLB_INFO
|
||||
.global _ipdt_swapcount_table; /* swapin count first, then swapout count */
|
||||
_ipdt_swapcount_table:
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 10 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 20 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 30 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 40 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 50 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 60 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 70 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 80 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 90 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 100 */
|
||||
|
||||
.global _dpdt_swapcount_table; /* swapin count first, then swapout count */
|
||||
_dpdt_swapcount_table:
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 10 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 20 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 30 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 40 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 50 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 60 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 70 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 80 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 80 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 100 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 110 */
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000;
|
||||
.byte4 0x00000000; /* 120 */
|
||||
|
||||
#endif
|
||||
|
||||
#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/
|
||||
|
|
@ -50,7 +50,7 @@
|
|||
|
||||
#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
|
||||
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
|
||||
|
||||
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
|
||||
|
|
@ -61,20 +61,20 @@
|
|||
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
|
||||
#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||
#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
|
||||
#else /*Write Through */
|
||||
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
|
||||
#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BF561)
|
||||
#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM +L1 + ASYNC_Memory */
|
||||
#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4) /* SDRAM +L1 + ASYNC_Memory */
|
||||
#else
|
||||
#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 3) /* SDRAM + L1 + ASYNC_Memory */
|
||||
#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM + L1 + ASYNC_Memory */
|
||||
#endif
|
||||
#endif /* _CPLB_H */
|
||||
|
|
|
|||
|
|
@ -182,7 +182,7 @@ void init_cplbtables(void)
|
|||
icplb_table[j][1] = L1_IMEMORY;
|
||||
j++;
|
||||
|
||||
for (i = 0; i <= CONFIG_MEM_SIZE / 4; i++) {
|
||||
for (i = 0; i < CONFIG_MEM_SIZE / 4; i++) {
|
||||
icplb_table[j][0] = (i * 4 * 1024 * 1024);
|
||||
if (i * 4 * 1024 * 1024 <= CFG_MONITOR_BASE
|
||||
&& (i + 1) * 4 * 1024 * 1024 >= CFG_MONITOR_BASE) {
|
||||
|
|
@ -193,14 +193,19 @@ void init_cplbtables(void)
|
|||
j++;
|
||||
}
|
||||
#if defined(CONFIG_BF561)
|
||||
/* MAC space */
|
||||
icplb_table[j][0] = 0x2C000000;
|
||||
icplb_table[j][1] = SDRAM_INON_CHBL;
|
||||
j++;
|
||||
/* Async Memory space */
|
||||
for (i = 0; i < 3; i++) {
|
||||
icplb_table[j++][0] = 0x20000000 + i * 4 * 1024 * 1024;
|
||||
icplb_table[j++][1] = SDRAM_IGENERIC;
|
||||
icplb_table[j][0] = 0x20000000 + i * 4 * 1024 * 1024;
|
||||
icplb_table[j][1] = SDRAM_INON_CHBL;
|
||||
j++;
|
||||
}
|
||||
#else
|
||||
icplb_table[j][0] = 0x20000000;
|
||||
icplb_table[j][1] = SDRAM_IGENERIC;
|
||||
icplb_table[j][1] = SDRAM_INON_CHBL;
|
||||
#endif
|
||||
j = 0;
|
||||
dcplb_table[j][0] = 0xFF800000;
|
||||
|
|
@ -220,13 +225,15 @@ void init_cplbtables(void)
|
|||
|
||||
#if defined(CONFIG_BF561)
|
||||
/* MAC space */
|
||||
dcplb_table[j++][0] = CONFIG_ASYNC_EBIU_BASE;
|
||||
dcplb_table[j++][1] = SDRAM_EBIU;
|
||||
dcplb_table[j][0] = 0x2C000000;
|
||||
dcplb_table[j][1] = SDRAM_EBIU;
|
||||
j++;
|
||||
|
||||
/* Flash space */
|
||||
for (i = 0; i < 2; i++) {
|
||||
dcplb_table[j++][0] = 0x20000000 + i * 4 * 1024 * 1024;
|
||||
dcplb_table[j++][1] = SDRAM_EBIU;
|
||||
for (i = 0; i < 3; i++) {
|
||||
dcplb_table[j][0] = 0x20000000 + i * 4 * 1024 * 1024;
|
||||
dcplb_table[j][1] = SDRAM_EBIU;
|
||||
j++;
|
||||
}
|
||||
#else
|
||||
dcplb_table[j][0] = 0x20000000;
|
||||
|
|
|
|||
Loading…
Reference in a new issue