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u-boot/arch/arm/mach-socfpga/include/mach/reset_manager.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
ARM: Add Altera SOCFPGA Cyclone5 Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Tom Trini <trini@ti.com> Cc: Wolfgang Denx <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2
2012-10-04 06:46:02 +00:00
/*
arm: socfpga: Restructure reset manager driver Restructure reset manager driver in the preparation to support A10. Move the Gen5 specific code to gen5 files. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:34 +00:00
* Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
ARM: Add Altera SOCFPGA Cyclone5 Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Tom Trini <trini@ti.com> Cc: Wolfgang Denx <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2
2012-10-04 06:46:02 +00:00
*/
arm: socfpga: Restructure reset manager driver Restructure reset manager driver in the preparation to support A10. Move the Gen5 specific code to gen5 files. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:34 +00:00
#ifndef _RESET_MANAGER_H_
#define _RESET_MANAGER_H_
ARM: Add Altera SOCFPGA Cyclone5 Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Tom Trini <trini@ti.com> Cc: Wolfgang Denx <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2
2012-10-04 06:46:02 +00:00
arm: socfpga: Convert reset manager from struct to defines Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get reset manager base address from DT node instead of using #define. spl_early_init() initializes the DT setup. So, move spl_early_init() to beginning of function and before get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-08 02:38:19 +00:00
phys_addr_t socfpga_get_rstmgr_addr(void);
reset: Remove addr parameter from reset_cpu() Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-15 15:47:52 +00:00
void reset_cpu(void);
arm: socfpga: reset: Add function to reset FPGA bridges Add function to enable and disable FPGA bridges. This code is used by the FPGA manager to disable the bridges before programming the FPGA and will later be also used by the initialization code for the chip to put the chip into well defined state during startup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-09-08 12:08:45 +00:00
arm: socfpga: reset: Implement unified function to toggle reset Implement function socfpga_per_reset(), which allows asserting or de-asserting reset of each reset manager peripheral in a unified manner. Use this function throughout reset manager. Signed-off-by: Marek Vasut <marex@denx.de>
2015-07-09 00:45:15 +00:00
void socfpga_per_reset(u32 reset, int set);
arm: socfpga: reset: Add function to reset add peripherals Add socfpga_per_reset_all() function to reset all peripherals but the L4 watchdog. This is needed in the SPL. Signed-off-by: Marek Vasut <marex@denx.de>
2015-07-09 02:27:28 +00:00
void socfpga_per_reset_all(void);
arm: socfpga: reset: Implement unified function to toggle reset Implement function socfpga_per_reset(), which allows asserting or de-asserting reset of each reset manager peripheral in a unified manner. Use this function throughout reset manager. Signed-off-by: Marek Vasut <marex@denx.de>
2015-07-09 00:45:15 +00:00
arm: socfpga: rst: add register definition for cold reset This adds a define for the bit in rstmgr's ctrl regiser that issues a cold reset (we had a define for the warm reset bit only) in preparation for a proper sysrese driver. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Series changes: 2 - separate this patch to the register descriptions from the actual sysreset driver patch
2019-07-15 19:47:52 +00:00
#define RSTMGR_CTRL_SWCOLDRSTREQ_LSB 0
ARM: Add Altera SOCFPGA Cyclone5 Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Tom Trini <trini@ti.com> Cc: Wolfgang Denx <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2
2012-10-04 06:46:02 +00:00
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
arm: socfpga: reset: Start reworking the SoCFPGA reset manager Implement macro SOCFPGA_RESET(name), which produces an abstract reset number. Implement macros which allow extracting the reset offset in permodrstN register and which permodrstN register the reset is located in from this abstract reset number. Use these macros throughout the reset manager. Signed-off-by: Marek Vasut <marex@denx.de>
2015-07-09 00:30:35 +00:00
/*
* Define a reset identifier, from which a permodrst bank ID
* and reset ID can be extracted using the subsequent macros
* RSTMGR_RESET() and RSTMGR_BANK().
*/
#define RSTMGR_BANK_OFFSET 8
#define RSTMGR_BANK_MASK 0x7
#define RSTMGR_RESET_OFFSET 0
#define RSTMGR_RESET_MASK 0x1f
#define RSTMGR_DEFINE(_bank, _offset) \
((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
/* Extract reset ID from the reset identifier. */
#define RSTMGR_RESET(_reset) \
(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
/* Extract bank ID from the reset identifier. */
#define RSTMGR_BANK(_reset) \
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
/* Create a human-readable reference to SoCFPGA reset. */
#define SOCFPGA_RESET(_name) RSTMGR_##_name
arm: socfpga: Add watchdog disable for socfpga This adds watchdog disable. It is neccessary for running Linux kernel. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
2014-09-09 12:03:28 +00:00
arm: socfpga: Restructure reset manager driver Restructure reset manager driver in the preparation to support A10. Move the Gen5 specific code to gen5 files. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:34 +00:00
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#include <asm/arch/reset_manager_gen5.h>
arm: socfpga: Add reset driver support for Arria 10 Add reset driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:38 +00:00
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#include <asm/arch/reset_manager_arria10.h>
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-03-01 12:04:10 +00:00
#elif defined(CONFIG_TARGET_SOCFPGA_SOC64)
arm: socfpga: Move Stratix10 and Agilex reset manager common code Move Stratix10 and Agilex reset manager common code to reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*. Remove unused RSTMGR_XXX defines. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-27 07:55:16 +00:00
#include <asm/arch/reset_manager_soc64.h>
arm: socfpga: Restructure reset manager driver Restructure reset manager driver in the preparation to support A10. Move the Gen5 specific code to gen5 files. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:34 +00:00
#endif
ARM: Add Altera SOCFPGA Cyclone5 Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Tom Trini <trini@ti.com> Cc: Wolfgang Denx <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2
2012-10-04 06:46:02 +00:00
#endif /* _RESET_MANAGER_H_ */
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