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u-boot/drivers/ram/k3-ddrss/lpddr4_structs_if.h

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ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 13:56:36 +00:00
/* SPDX-License-Identifier: BSD-3-Clause */
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-11 15:22:11 +00:00
/*
* Cadence DDR Driver
*
ram: k3-ddrss: add auto-generated macros for am62a support The new 32bit DDR controller for TI's am62a family of SoCs shares much of the same functionality with the existing 16bit (am64) and 32bit (j721e) controllers, so this patch reorganizes the existing auto-generated macros for the 16bit and 32bit controllers to make room for the macros for the am62a's controller This patch consists mostly of header/macro renames and additions with a new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new macros during compilation. Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-10-24 21:53:28 +00:00
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 13:56:36 +00:00
*/
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-11 15:22:11 +00:00
ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 13:56:36 +00:00
#ifndef LPDDR4_STRUCTS_IF_H
#define LPDDR4_STRUCTS_IF_H
#include <linux/types.h>
#include "lpddr4_if.h"
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-11 15:22:11 +00:00
struct lpddr4_config_s {
struct lpddr4_ctlregs_s *ctlbase;
ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 13:56:36 +00:00
lpddr4_infocallback infohandler;
lpddr4_ctlcallback ctlinterrupthandler;
lpddr4_phyindepcallback phyindepinterrupthandler;
};
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-11 15:22:11 +00:00
struct lpddr4_privatedata_s {
struct lpddr4_ctlregs_s *ctlbase;
ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 13:56:36 +00:00
lpddr4_infocallback infohandler;
lpddr4_ctlcallback ctlinterrupthandler;
lpddr4_phyindepcallback phyindepinterrupthandler;
ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance Add a pointer to ddr instance int the lpddr4_privatedata_s structure for supporting mutliple instances of DDR in the drivers. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-01-25 15:26:28 +00:00
void *ddr_instance;
ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 13:56:36 +00:00
};
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-11 15:22:11 +00:00
struct lpddr4_debuginfo_s {
u8 pllerror;
u8 iocaliberror;
u8 rxoffseterror;
u8 catraingerror;
u8 wrlvlerror;
u8 gatelvlerror;
u8 readlvlerror;
u8 dqtrainingerror;
ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 13:56:36 +00:00
};
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-11 15:22:11 +00:00
struct lpddr4_fspmoderegs_s {
u8 mr1data_fn[LPDDR4_INTR_MAX_CS];
u8 mr2data_fn[LPDDR4_INTR_MAX_CS];
u8 mr3data_fn[LPDDR4_INTR_MAX_CS];
u8 mr11data_fn[LPDDR4_INTR_MAX_CS];
u8 mr12data_fn[LPDDR4_INTR_MAX_CS];
u8 mr13data_fn[LPDDR4_INTR_MAX_CS];
u8 mr14data_fn[LPDDR4_INTR_MAX_CS];
u8 mr22data_fn[LPDDR4_INTR_MAX_CS];
ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 13:56:36 +00:00
};
#endif /* LPDDR4_STRUCTS_IF_H */
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