2014-11-13 18:21:18 +00:00
|
|
|
CONFIG_PPC=y
|
2018-02-03 17:10:38 +00:00
|
|
|
CONFIG_SYS_TEXT_BASE=0xFE000000
|
2019-11-19 01:02:10 +00:00
|
|
|
CONFIG_ENV_SIZE=0x2000
|
|
|
|
CONFIG_ENV_SECT_SIZE=0x10000
|
2016-07-29 10:01:47 +00:00
|
|
|
CONFIG_IDENT_STRING=" hrcon 0.01"
|
2019-01-21 08:17:53 +00:00
|
|
|
CONFIG_SYS_CLK_FREQ=33333333
|
2014-11-13 18:21:18 +00:00
|
|
|
CONFIG_MPC83xx=y
|
|
|
|
CONFIG_TARGET_HRCON=y
|
2019-01-21 08:17:54 +00:00
|
|
|
CONFIG_SYSTEM_PLL_VCO_DIV_2=y
|
|
|
|
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
|
|
|
|
CONFIG_CORE_PLL_RATIO_3_1=y
|
|
|
|
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
|
|
|
|
CONFIG_TSEC1_MODE_RGMII=y
|
|
|
|
CONFIG_TSEC2_MODE_RGMII=y
|
2019-01-21 08:17:57 +00:00
|
|
|
CONFIG_BAT0=y
|
|
|
|
CONFIG_BAT0_NAME="DDR"
|
|
|
|
CONFIG_BAT0_BASE=0x00000000
|
|
|
|
CONFIG_BAT0_LENGTH_128_MBYTES=y
|
|
|
|
CONFIG_BAT0_ACCESS_RW=y
|
|
|
|
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
|
|
|
|
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
|
|
|
|
CONFIG_BAT0_USER_MODE_VALID=y
|
|
|
|
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
|
|
|
|
CONFIG_BAT1=y
|
|
|
|
CONFIG_BAT1_NAME="IMMRBAR"
|
|
|
|
CONFIG_BAT1_BASE=0xE0000000
|
|
|
|
CONFIG_BAT1_LENGTH_8_MBYTES=y
|
|
|
|
CONFIG_BAT1_ACCESS_RW=y
|
|
|
|
CONFIG_BAT1_ICACHE_INHIBITED=y
|
|
|
|
CONFIG_BAT1_ICACHE_GUARDED=y
|
|
|
|
CONFIG_BAT1_DCACHE_INHIBITED=y
|
|
|
|
CONFIG_BAT1_DCACHE_GUARDED=y
|
|
|
|
CONFIG_BAT1_USER_MODE_VALID=y
|
|
|
|
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
|
|
|
|
CONFIG_BAT2=y
|
|
|
|
CONFIG_BAT2_NAME="FLASH"
|
|
|
|
CONFIG_BAT2_BASE=0xFE000000
|
|
|
|
CONFIG_BAT2_LENGTH_8_MBYTES=y
|
|
|
|
CONFIG_BAT2_ACCESS_RW=y
|
|
|
|
CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
|
|
|
|
CONFIG_BAT2_DCACHE_INHIBITED=y
|
|
|
|
CONFIG_BAT2_DCACHE_GUARDED=y
|
|
|
|
CONFIG_BAT2_USER_MODE_VALID=y
|
|
|
|
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
|
|
|
|
CONFIG_BAT3=y
|
|
|
|
CONFIG_BAT3_NAME="STACK_IN_DCACHE"
|
|
|
|
CONFIG_BAT3_BASE=0xE6000000
|
|
|
|
CONFIG_BAT3_ACCESS_RW=y
|
|
|
|
CONFIG_BAT3_USER_MODE_VALID=y
|
|
|
|
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
|
2019-01-21 08:17:58 +00:00
|
|
|
CONFIG_LBLAW0=y
|
|
|
|
CONFIG_LBLAW0_BASE=0xFE000000
|
|
|
|
CONFIG_LBLAW0_NAME="FLASH"
|
|
|
|
CONFIG_LBLAW0_LENGTH_8_MBYTES=y
|
|
|
|
CONFIG_LBLAW1=y
|
|
|
|
CONFIG_LBLAW1_BASE=0xE0600000
|
|
|
|
CONFIG_LBLAW1_NAME="FPGA0"
|
|
|
|
CONFIG_LBLAW1_LENGTH_1_MBYTES=y
|
2019-05-26 18:45:25 +00:00
|
|
|
CONFIG_ELBC_BR0_OR0=y
|
|
|
|
CONFIG_BR0_OR0_NAME="FLASH"
|
|
|
|
CONFIG_BR0_OR0_BASE=0xFE000000
|
|
|
|
CONFIG_BR0_PORTSIZE_16BIT=y
|
|
|
|
CONFIG_OR0_AM_8_MBYTES=y
|
|
|
|
CONFIG_OR0_XAM_SET=y
|
|
|
|
CONFIG_OR0_SCY_15=y
|
|
|
|
CONFIG_OR0_CSNT_EARLIER=y
|
|
|
|
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
|
|
|
|
CONFIG_OR0_XACS_EXTENDED=y
|
|
|
|
CONFIG_OR0_TRLX_RELAXED=y
|
|
|
|
CONFIG_OR0_EHTR_8_CYCLE=y
|
|
|
|
CONFIG_ELBC_BR1_OR1=y
|
|
|
|
CONFIG_BR1_OR1_NAME="FPGA"
|
|
|
|
CONFIG_BR1_OR1_BASE=0xE0600000
|
|
|
|
CONFIG_BR1_PORTSIZE_16BIT=y
|
|
|
|
CONFIG_OR1_AM_1_MBYTES=y
|
|
|
|
CONFIG_OR1_XAM_SET=y
|
|
|
|
CONFIG_OR1_SCY_15=y
|
|
|
|
CONFIG_OR1_CSNT_EARLIER=y
|
|
|
|
CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
|
|
|
|
CONFIG_OR1_XACS_EXTENDED=y
|
|
|
|
CONFIG_OR1_TRLX_RELAXED=y
|
|
|
|
CONFIG_OR1_EHTR_8_CYCLE=y
|
2019-01-21 08:18:09 +00:00
|
|
|
CONFIG_HID0_FINAL_EMCP=y
|
|
|
|
CONFIG_HID0_FINAL_DPM=y
|
|
|
|
CONFIG_HID0_FINAL_ICE=y
|
|
|
|
CONFIG_HID2_HBE=y
|
2019-01-21 08:18:11 +00:00
|
|
|
CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
|
|
|
|
CONFIG_SICR_IEEE1588_A_GPIO=y
|
|
|
|
CONFIG_SICR_GTM_GPIO=y
|
|
|
|
CONFIG_SICR_ETSEC2_GPIO=y
|
|
|
|
CONFIG_SICR_GPIOSEL_IEEE1588=y
|
|
|
|
CONFIG_SICR_TMSOBI1_2_5_V=y
|
|
|
|
CONFIG_SICR_TMSOBI2_2_5_V=y
|
2019-01-21 08:18:12 +00:00
|
|
|
CONFIG_ACR_PIPE_DEP_4=y
|
|
|
|
CONFIG_ACR_RPTCNT_4=y
|
2019-01-21 08:18:13 +00:00
|
|
|
CONFIG_SPCR_TSECEP_3=y
|
2019-05-26 18:45:25 +00:00
|
|
|
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
|
|
|
|
CONFIG_LCRR_CLKDIV_2=y
|
2017-05-17 09:25:35 +00:00
|
|
|
CONFIG_CMD_IOLOOP=y
|
2016-02-23 05:55:43 +00:00
|
|
|
CONFIG_FIT=y
|
|
|
|
CONFIG_FIT_VERBOSE=y
|
|
|
|
CONFIG_OF_BOARD_SETUP=y
|
|
|
|
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
2016-06-07 06:31:14 +00:00
|
|
|
CONFIG_BOOTDELAY=5
|
2019-07-21 02:51:14 +00:00
|
|
|
CONFIG_USE_PREBOOT=y
|
2016-10-18 02:13:00 +00:00
|
|
|
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
2016-10-12 01:33:46 +00:00
|
|
|
# CONFIG_DISPLAY_BOARDINFO is not set
|
2017-01-23 20:31:20 +00:00
|
|
|
CONFIG_BOARD_EARLY_INIT_F=y
|
2018-03-28 12:38:15 +00:00
|
|
|
CONFIG_BOARD_EARLY_INIT_R=y
|
2018-03-28 12:38:16 +00:00
|
|
|
CONFIG_LAST_STAGE_INIT=y
|
2016-04-22 01:37:19 +00:00
|
|
|
CONFIG_HUSH_PARSER=y
|
2015-05-18 12:08:23 +00:00
|
|
|
CONFIG_AUTOBOOT_KEYED=y
|
|
|
|
CONFIG_AUTOBOOT_STOP_STR=" "
|
2017-10-08 18:48:01 +00:00
|
|
|
CONFIG_CMD_IMLS=y
|
2017-05-17 09:25:20 +00:00
|
|
|
CONFIG_CMD_FPGAD=y
|
2017-08-14 23:58:53 +00:00
|
|
|
CONFIG_CMD_I2C=y
|
|
|
|
CONFIG_CMD_MMC=y
|
2017-08-04 22:34:34 +00:00
|
|
|
CONFIG_CMD_PCI=y
|
2015-06-22 21:15:30 +00:00
|
|
|
# CONFIG_CMD_SETEXPR is not set
|
2016-04-24 21:29:26 +00:00
|
|
|
CONFIG_CMD_MII=y
|
2016-04-22 20:41:25 +00:00
|
|
|
CONFIG_CMD_PING=y
|
2016-04-24 21:29:26 +00:00
|
|
|
CONFIG_CMD_EXT2=y
|
2017-01-27 10:00:37 +00:00
|
|
|
CONFIG_DOS_PARTITION=y
|
2019-11-10 16:28:03 +00:00
|
|
|
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
2019-11-19 01:02:10 +00:00
|
|
|
CONFIG_ENV_ADDR=0xFE060000
|
|
|
|
CONFIG_ENV_ADDR_REDUND=0xFE070000
|
2018-03-28 12:38:19 +00:00
|
|
|
CONFIG_FSL_ESDHC=y
|
2017-02-11 13:43:54 +00:00
|
|
|
CONFIG_MTD_NOR_FLASH=y
|
2018-10-14 20:10:50 +00:00
|
|
|
CONFIG_FLASH_CFI_DRIVER=y
|
|
|
|
CONFIG_SYS_FLASH_PROTECTION=y
|
|
|
|
CONFIG_SYS_FLASH_CFI=y
|
2018-04-27 12:52:21 +00:00
|
|
|
CONFIG_PHY_MARVELL=y
|
2018-07-21 04:03:57 +00:00
|
|
|
CONFIG_MII=y
|
2018-03-28 12:38:18 +00:00
|
|
|
CONFIG_TSEC_ENET=y
|
2018-03-07 00:02:27 +00:00
|
|
|
CONFIG_CONS_INDEX=2
|
2015-11-19 13:48:14 +00:00
|
|
|
CONFIG_SYS_NS16550=y
|
2016-02-23 05:55:42 +00:00
|
|
|
CONFIG_OF_LIBFDT=y
|