2018-05-18 14:05:22 +00:00
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#ifndef _HANDOFF_S10_H_
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#define _HANDOFF_S10_H_
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/*
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* Offset for HW handoff from Quartus tools
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*/
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#define S10_HANDOFF_BASE 0xFFE3F000
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#define S10_HANDOFF_MUX (S10_HANDOFF_BASE + 0x10)
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#define S10_HANDOFF_IOCTL (S10_HANDOFF_BASE + 0x1A0)
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#define S10_HANDOFF_FPGA (S10_HANDOFF_BASE + 0x330)
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#define S10_HANODFF_DELAY (S10_HANDOFF_BASE + 0x3F0)
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#define S10_HANDOFF_CLOCK (S10_HANDOFF_BASE + 0x580)
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#define S10_HANDOFF_MISC (S10_HANDOFF_BASE + 0x610)
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#define S10_HANDOFF_MAGIC_MUX 0x504D5558
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#define S10_HANDOFF_MAGIC_IOCTL 0x494F4354
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#define S10_HANDOFF_MAGIC_FPGA 0x46504741
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#define S10_HANDOFF_MAGIC_DELAY 0x444C4159
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#define S10_HANDOFF_MAGIC_CLOCK 0x434C4B53
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#define S10_HANDOFF_MAGIC_MISC 0x4D495343
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#define S10_HANDOFF_OFFSET_LENGTH 0x4
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#define S10_HANDOFF_OFFSET_DATA 0x10
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2019-11-27 07:55:25 +00:00
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#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
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#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608)
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#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C)
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#else
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#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x5fc)
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#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x600)
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#endif
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2018-05-18 14:05:22 +00:00
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#define S10_HANDOFF_SIZE 4096
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#endif /* _HANDOFF_S10_H_ */
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