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u-boot/drivers/pinctrl/Makefile

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Various Makefiles: Add SPDX-License-Identifier tags After consulting with some of the SPDX team, the conclusion is that Makefiles are worth adding SPDX-License-Identifier tags too, and most of ours have one. This adds tags to ones that lack them and converts a few that had full (or in one case, very partial) license blobs into the equivalent tag. Cc: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2015-11-10 01:06:16 +00:00
#
# SPDX-License-Identifier: GPL-2.0+
#
pinctrl: add pin control uclass support This creates a new framework for handling of pin control devices, i.e. devices that control different aspects of package pins. This uclass handles pinmuxing and pin configuration; pinmuxing controls switching among silicon blocks that share certain physical pins, pin configuration handles electronic properties such as pin- biasing, load capacitance etc. This framework can support the same device tree bindings, but if you do not need full interface support, you can disable some features to reduce memory foot print. Typically around 1.5KB is necessary to include full-featured uclass support on ARM board (CONFIG_PINCTRL + CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX), for example. We are often limited on code size for SPL. Besides, we still have many boards that do not support device tree configuration. The full pinctrl, which requires OF_CONTROL, does not make sense for those boards. So, this framework also has a Do-It-Yourself (let's say simple pinctrl) interface. With CONFIG_PINCTRL_FULL disabled, the uclass itself provides no systematic mechanism for identifying the peripheral device, applying pinctrl settings, etc. They must be done in each low-level driver. In return, you can save much memory footprint and it might be useful especially for SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-08-27 03:44:29 +00:00
obj-y += pinctrl-uclass.o
obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o
pinctrl: sandbox: add sandbox pinctrl driver This driver actually does nothing but test pinctrl uclass, and demonstrate how things work. To try this driver, uncomment /* #define DEBUG */ in the drivers/pinctrl/pinctrl-sandbox.c, and debug messages will be displayed. DRAM: 128 MiB sandbox pinmux: group = 1 (serial_a), function = 1 (serial) Using default environment In: cros-ec-keyb Out: lcd Err: lcd Net: Net Initialization Skipped eth0: eth@10002000, eth1: eth@80000000, eth5: eth@90000000 => i2c dev 0 Setting bus to 0 sandbox pinmux: group = 0 (i2c), function = 0 (i2c) sandbox pinconf: group = 0 (i2c), param = 3, arg = 1 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-08-27 03:44:30 +00:00
pinctrl: at91: add pinctrl driver AT91 PIO controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. Each SoC will have to describe the its limitation and pin configuration via device tree. This will allow to do not need to touch the C code when adding new SoC if the IP version is supported. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-23 04:44:37 +00:00
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
pinctrl: at91-pio4: Add pinctrl driver AT91 PIO4 controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. The pin configuration is performed on specific registers which are shared along with the gpio controller. So regard the pinctrl device as a child of atmel_pio4 device. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-07-20 09:16:27 +00:00
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
pinctrl: imx: Introduce pinctrl driver for i.MX6 Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-03 02:06:07 +00:00
obj-y += nxp/
drivers: pinctrl: Add simple pinctrl driver for Qualcomm/Atheros ar933x. This is a simple pinctrl driver, it just support uart and spi pin-mux now. Signed-off-by: Wills Wang <wills.wang@live.com> Reviewed-by: Simon Glass <sjg@chromium.org> [fixed typo in commit subject line] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-03-16 08:59:55 +00:00
obj-$(CONFIG_ARCH_ATH79) += ath79/
rockchip: rk3288: Add pinctrl driver Add a driver which supports pin multiplexing setup for the most commonly used peripherals. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:35 +00:00
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
pinctrl: sandbox: add sandbox pinctrl driver This driver actually does nothing but test pinctrl uclass, and demonstrate how things work. To try this driver, uncomment /* #define DEBUG */ in the drivers/pinctrl/pinctrl-sandbox.c, and debug messages will be displayed. DRAM: 128 MiB sandbox pinmux: group = 1 (serial_a), function = 1 (serial) Using default environment In: cros-ec-keyb Out: lcd Err: lcd Net: Net Initialization Skipped eth0: eth@10002000, eth1: eth@80000000, eth5: eth@90000000 => i2c dev 0 Setting bus to 0 sandbox pinmux: group = 0 (i2c), function = 0 (i2c) sandbox pinconf: group = 0 (i2c), param = 3, arg = 1 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-08-27 03:44:30 +00:00
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
pinctrl: uniphier: add UniPhier pinctrl core support The core support for the pinctrl drivers for all the UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-11 11:17:32 +00:00
pinctrl: uniphier: guard uniphier directory with CONFIG_PINCTRL_UNIPHIER CONFIG_PINCTRL_UNIPHIER is more suitable than CONFIG_ARCH_UNIPHIER to guard the drivers/pinctrl/uniphier directory. The current CONFIG_PINCTRL_UNIPHIER_CORE is a bit long, so rename it into CONFIG_PINCTRL_UNIPHIER. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-04 06:56:31 +00:00
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
drivers: pinctrl: Add pinctrl driver for Microchip PIC32. In PIC32 pin-controller is a combined gpio-controller, pin-mux and pin-config module. Remappable peripherals are assigned pins through per-pin based muxing logic. And pin configuration are performed on specific port registers which are shared along with gpio controller. Note, non-remappable peripherals have default pins assigned thus require no muxing. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-28 10:00:12 +00:00
obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o
pinctrl: Add pinctrl driver support for Exynos7420 SoC Add pinctrl driver support for Samsung's Exynos7420 SoC. The changes have been split into Exynos7420 specific and common Exynos specific portions so that this implementation is reusable on other Exynos SoCs as well. The Exynos pinctrl driver supports only device tree based pin configuration. The bindings used are similar to the ones used in the linux kernel. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2016-04-23 16:48:08 +00:00
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
pinctrl: add driver for meson-gxbb pin controller Add a pin controller driver for Meson GXBB adapted from Linux kernel. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-16 09:49:49 +00:00
obj-$(CONFIG_PINCTRL_MESON) += meson/
arm64: mvebu: pinctrl: Add pin control driver for A8K family Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-08 10:22:29 +00:00
obj-$(CONFIG_PINCTRL_MVEBU) += mvebu/
Add single register pin controller driver This patch adds a pin controller driver supporting devices using a single configuration register per pin. Signed-off-by: Felix Brack <fb@ltec.ch>
2017-03-22 10:26:44 +00:00
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
STiH410: Add STi pinctrl driver Add STMicroelectronics STiH410 pinctrl driver Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-02-21 12:37:10 +00:00
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
PINCTRL: stm32f7: add pin control driver This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-02-12 18:25:49 +00:00
obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o
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