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45 lines
1.1 KiB
C
45 lines
1.1 KiB
C
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/*
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* K2E: SoC definitions
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_HARDWARE_K2E_H
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#define __ASM_ARCH_HARDWARE_K2E_H
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/* PA SS Registers */
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#define KS2_PASS_BASE 0x24000000
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/* Power and Sleep Controller (PSC) Domains */
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#define KS2_LPSC_MOD_RST 0
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#define KS2_LPSC_USB_1 1
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#define KS2_LPSC_USB 2
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#define KS2_LPSC_EMIF25_SPI 3
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#define KS2_LPSC_TSIP 4
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#define KS2_LPSC_DEBUGSS_TRC 5
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#define KS2_LPSC_TETB_TRC 6
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#define KS2_LPSC_PKTPROC 7
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#define KS2_LPSC_PA KS2_LPSC_PKTPROC
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#define KS2_LPSC_SGMII 8
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#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
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#define KS2_LPSC_CRYPTO 9
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#define KS2_LPSC_PCIE 10
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#define KS2_LPSC_VUSR0 12
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#define KS2_LPSC_CHIP_SRSS 13
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#define KS2_LPSC_MSMC 14
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#define KS2_LPSC_EMIF4F_DDR3 23
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#define KS2_LPSC_PCIE_1 27
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#define KS2_LPSC_XGE 50
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/* Chip Interrupt Controller */
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#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
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#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
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/* Number of DSP cores */
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#define KS2_NUM_DSPS 1
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#endif
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