2020-04-21 07:28:49 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef __CONFIG_MT7628_H
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#define __CONFIG_MT7628_H
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#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_INIT_SP_OFFSET 0x80000
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#define CONFIG_SYS_BOOTM_LEN 0x1000000
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/* Serial SPL */
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2021-08-08 18:20:12 +00:00
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
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2020-04-21 07:28:49 +00:00
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_SYS_NS16550_CLK 40000000
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_SYS_NS16550_COM1 0xb0000c00
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#endif
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/* Serial common */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
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230400, 460800, 921600 }
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/* SPL */
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#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SPL_BSS_START_ADDR 0x80010000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
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#define CONFIG_SPL_MAX_SIZE 0x10000
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#define CONFIG_SPL_PAD_TO 0
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/* Dummy value */
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#define CONFIG_SYS_UBOOT_BASE 0
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#endif /* __CONFIG_MT7628_H */
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