2012-05-02 13:48:51 +00:00
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/*
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2012-05-21 11:08:03 +00:00
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* SAMSUNG EXYNOS USB HOST EHCI Controller
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2012-05-02 13:48:51 +00:00
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*
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* Copyright (C) 2012 Samsung Electronics Co.Ltd
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* Vivek Gautam <gautam.vivek@samsung.com>
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2012-05-02 13:48:51 +00:00
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*/
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2012-05-21 11:08:03 +00:00
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#ifndef __ASM_ARM_ARCH_EHCI_H__
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#define __ASM_ARM_ARCH_EHCI_H__
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2012-05-02 13:48:51 +00:00
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#define CLK_24MHZ 5
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#define HOST_CTRL0_PHYSWRSTALL (1 << 31)
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#define HOST_CTRL0_COMMONON_N (1 << 9)
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#define HOST_CTRL0_SIDDQ (1 << 6)
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#define HOST_CTRL0_FORCESLEEP (1 << 5)
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#define HOST_CTRL0_FORCESUSPEND (1 << 4)
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#define HOST_CTRL0_WORDINTERFACE (1 << 3)
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#define HOST_CTRL0_UTMISWRST (1 << 2)
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#define HOST_CTRL0_LINKSWRST (1 << 1)
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#define HOST_CTRL0_PHYSWRST (1 << 0)
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#define HOST_CTRL0_FSEL_MASK (7 << 16)
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#define EHCICTRL_ENAINCRXALIGN (1 << 29)
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#define EHCICTRL_ENAINCR4 (1 << 28)
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#define EHCICTRL_ENAINCR8 (1 << 27)
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#define EHCICTRL_ENAINCR16 (1 << 26)
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/* Register map for PHY control */
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2012-05-21 11:08:03 +00:00
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struct exynos_usb_phy {
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2012-05-02 13:48:51 +00:00
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unsigned int usbphyctrl0;
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unsigned int usbphytune0;
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unsigned int reserved1[2];
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unsigned int hsicphyctrl1;
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unsigned int hsicphytune1;
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unsigned int reserved2[2];
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unsigned int hsicphyctrl2;
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unsigned int hsicphytune2;
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unsigned int reserved3[2];
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unsigned int ehcictrl;
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unsigned int ohcictrl;
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unsigned int usbotgsys;
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unsigned int reserved4;
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unsigned int usbotgtune;
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};
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/* Switch on the VBUS power. */
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int board_usb_vbus_init(void);
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2012-05-21 11:08:03 +00:00
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#endif /* __ASM_ARM_ARCH_EHCI_H__ */
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