2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2016-03-31 18:51:36 +00:00
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/*
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* include/configs/rcar-gen3-common.h
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* This file is R-Car Gen3 common configuration file.
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*
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2017-05-13 13:57:39 +00:00
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* Copyright (C) 2015-2017 Renesas Electronics Corporation
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2016-03-31 18:51:36 +00:00
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*/
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#ifndef __RCAR_GEN3_COMMON_H
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#define __RCAR_GEN3_COMMON_H
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#include <asm/arch/rmobile.h>
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#define CONFIG_REMAKE_ELF
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ARM: rmobile: Add recovery SPL for R-Car Gen3
Build an SPL which can be started via SCIF download mode on R-Car Gen3
and allows loading and executing U-Boot uImage with the next stage code.
This is also useful for starting e.g. ATF BL2, which inits the hardware
and returns to the U-Boot SPL, which can then load e.g. U-Boot proper.
The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL
while the payload, e.g. ATF BL2, executes, so there is no problem here.
However, E3 and D3 have much less SRAM, hence the loader uses a trick
where it copies itself beyond the area used by BL2 and executes from
there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS,
stack and malloc area, so the later two are placed at +0x4000 offset
from start of SRAM, another area not used by ATF BL2. To make things
even more complicated, the SCIF loader cannot load to the upper 32kiB
of the SRAM directly, hence the copying approach.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 10:44:13 +00:00
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#ifdef CONFIG_SPL
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#define CONFIG_SPL_TARGET "spl/u-boot-spl.scif"
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#endif
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2016-03-31 18:51:36 +00:00
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/* boot option */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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2017-11-28 07:25:21 +00:00
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/* Generic Interrupt Controller Definitions */
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#define CONFIG_GICV2
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#define GICD_BASE 0xF1010000
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#define GICC_BASE 0xF1020000
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2016-03-31 18:51:36 +00:00
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/* console */
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2017-07-21 21:16:08 +00:00
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#define CONFIG_SYS_CBSIZE 2048
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MAXARGS 64
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2016-03-31 18:51:36 +00:00
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 }
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2020-06-14 12:41:07 +00:00
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/* PHY needs a longer autoneg timeout */
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#define PHY_ANEG_TIMEOUT 20000
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2016-03-31 18:51:36 +00:00
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/* MEMORY */
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2017-09-15 19:09:47 +00:00
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
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2016-03-31 18:51:36 +00:00
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2017-05-13 13:57:39 +00:00
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#define DRAM_RSV_SIZE 0x08000000
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2017-11-27 05:01:20 +00:00
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#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
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#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
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2018-05-31 13:18:18 +00:00
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#define CONFIG_SYS_LOAD_ADDR 0x58000000
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#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
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2017-05-13 13:57:39 +00:00
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#define CONFIG_VERY_BIG_RAM
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2017-11-27 05:01:20 +00:00
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#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
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2016-03-31 18:51:36 +00:00
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#define CONFIG_SYS_MONITOR_BASE 0x00000000
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2020-01-24 00:31:37 +00:00
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#define CONFIG_SYS_MONITOR_LEN (1 * 1024 * 1024)
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2020-04-04 10:45:03 +00:00
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#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
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2018-04-10 14:06:40 +00:00
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#define CONFIG_SYS_BOOTM_LEN (64 << 20)
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2016-03-31 18:51:36 +00:00
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2020-01-24 00:31:37 +00:00
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/* The HF/QSPI layout permits up to 1 MiB large bootloader blob */
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#define CONFIG_BOARD_SIZE_LIMIT 1048576
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2016-03-31 18:51:36 +00:00
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/* ENV setting */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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2018-11-26 23:19:03 +00:00
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"bootm_size=0x10000000\0"
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2016-03-31 18:51:36 +00:00
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#define CONFIG_BOOTCOMMAND \
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"tftp 0x48080000 Image; " \
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2017-05-13 13:57:43 +00:00
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"tftp 0x48000000 Image-"CONFIG_DEFAULT_FDT_FILE"; " \
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2016-03-31 18:51:36 +00:00
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"booti 0x48080000 - 0x48000000"
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ARM: rmobile: Add recovery SPL for R-Car Gen3
Build an SPL which can be started via SCIF download mode on R-Car Gen3
and allows loading and executing U-Boot uImage with the next stage code.
This is also useful for starting e.g. ATF BL2, which inits the hardware
and returns to the U-Boot SPL, which can then load e.g. U-Boot proper.
The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL
while the payload, e.g. ATF BL2, executes, so there is no problem here.
However, E3 and D3 have much less SRAM, hence the loader uses a trick
where it copies itself beyond the area used by BL2 and executes from
there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS,
stack and malloc area, so the later two are placed at +0x4000 offset
from start of SRAM, another area not used by ATF BL2. To make things
even more complicated, the SCIF loader cannot load to the upper 32kiB
of the SRAM directly, hence the copying approach.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 10:44:13 +00:00
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/* SPL support */
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#if defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796) || defined(CONFIG_R8A77965)
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#define CONFIG_SPL_BSS_START_ADDR 0xe633f000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x1000
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#else
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#define CONFIG_SPL_BSS_START_ADDR 0xe631f000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x1000
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#endif
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#define CONFIG_SPL_STACK 0xe6304000
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#define CONFIG_SPL_MAX_SIZE 0x7000
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_CONS_SCIF2
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#define CONFIG_SH_SCIF_CLK_FREQ 65000000
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#endif
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2016-03-31 18:51:36 +00:00
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#endif /* __RCAR_GEN3_COMMON_H */
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