u-boot/arch/mips/mach-octeon/lowlevel_init.S

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2020 Stefan Roese <sr@denx.de>
 */

#include <config.h>
#include <asm-offsets.h>
#include <asm/cacheops.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/asm.h>

	.set noreorder

LEAF(lowlevel_init)
	jr	ra
	 nop
	END(lowlevel_init)
mips: octeon: Initial minimal support for the Marvell Octeon SoC This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> 2020-06-30 10:08:56 +00:00			`/* SPDX-License-Identifier: GPL-2.0 */`
			`/*`
			`* Copyright (C) 2020 Stefan Roese <sr@denx.de>`
			`*/`

			`#include <config.h>`
			`#include <asm-offsets.h>`
			`#include <asm/cacheops.h>`
			`#include <asm/regdef.h>`
			`#include <asm/mipsregs.h>`
			`#include <asm/addrspace.h>`
			`#include <asm/asm.h>`

			`.set noreorder`

			`LEAF(lowlevel_init)`
			`jr ra`
			`nop`
			`END(lowlevel_init)`