2012-04-19 04:33:08 +00:00
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/*
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* Common definitions for LPC32XX board configurations
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*
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2015-02-11 22:24:20 +00:00
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* Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
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2012-04-19 04:33:08 +00:00
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2012-04-19 04:33:08 +00:00
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*/
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#ifndef _LPC32XX_CONFIG_H
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#define _LPC32XX_CONFIG_H
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2015-02-11 22:24:20 +00:00
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#define CONFIG_SYS_GENERIC_BOARD
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2012-04-19 04:33:08 +00:00
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/* Basic CPU architecture */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_NR_DRAM_BANKS_MAX 2
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/* UART configuration */
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#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6)
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2)
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#elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
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(CONFIG_SYS_LPC32XX_UART == 7)
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#define CONFIG_LPC32XX_HSUART
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#else
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#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7"
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#endif
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#if defined(CONFIG_SYS_NS16550_SERIAL)
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#define CONFIG_SYS_NS16550_COM1 UART3_BASE
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#define CONFIG_SYS_NS16550_COM2 UART4_BASE
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#define CONFIG_SYS_NS16550_COM3 UART5_BASE
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#define CONFIG_SYS_NS16550_COM4 UART6_BASE
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#endif
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#if defined(CONFIG_LPC32XX_HSUART)
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#if CONFIG_SYS_LPC32XX_UART == 1
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#define HS_UART_BASE HS_UART1_BASE
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#elif CONFIG_SYS_LPC32XX_UART == 2
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#define HS_UART_BASE HS_UART2_BASE
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#else /* CONFIG_SYS_LPC32XX_UART == 7 */
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#define HS_UART_BASE HS_UART7_BASE
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#endif
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#endif
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
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/* NOR Flash */
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#if defined(CONFIG_SYS_FLASH_CFI)
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_PROTECTION
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#endif
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#endif /* _LPC32XX_CONFIG_H */
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