Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-18 02:38:56 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/arch/x86/dts/cougarcanyon2.dts

189 lines
3.6 KiB
Text
Raw Normal View History

SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
x86: Add Intel Cougar Canyon 2 board This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-02-17 08:16:25 +00:00
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*/
/dts-v1/;
x86: cougarcanyon2: Add missing chipset interrupt information Add Panther Point chipset interrupt pin/PIRQ information, and enable the generation of PIRQ routing table and MP table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-12 08:26:47 +00:00
#include <dt-bindings/interrupt-router/intel-irq.h>
x86: Add Intel Cougar Canyon 2 board This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-02-17 08:16:25 +00:00
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
x86: Switch to use DM sysreset driver This converts all x86 boards over to DM sysreset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-07-19 10:07:33 +00:00
/include/ "reset.dtsi"
x86: Add Intel Cougar Canyon 2 board This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-02-17 08:16:25 +00:00
/include/ "rtc.dtsi"
x86: dts: Define a default TSC timer frequency If for some reason, TSC timer frequency cannot be determined from hardware, nor is it specified in the device tree, U-Boot will panic resulting in endless reset during boot. Let's define a default TSC timer frequency using the Kconfig value CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of /include/ otherwise the macro is not pre-processed). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-28 04:00:23 +00:00
#include "tsc_timer.dtsi"
x86: Provide default SMBIOS manufacturer/product Add a file containing defaults for these, using the existing CONFIG options. This file must be included with #include since it needs to be passed through the C preprocessor. Enable the driver for all x86 boards that generate SMBIOS tables. Disable it for coral since it has its own driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: reword the commit message a little bit] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 13:32:17 +00:00
#include "smbios.dtsi"
x86: Add Intel Cougar Canyon 2 board This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-02-17 08:16:25 +00:00
/ {
model = "Intel Cougar Canyon 2";
compatible = "intel,cougarcanyon2", "intel,chiefriver";
aliases {
spi0 = &spi0;
};
config {
silent_console = <0>;
};
chosen {
stdout-path = "/serial";
};
x86: cougarcanyon2: Enable CPU driver and SMP support This enables the 206ax cpu driver on Intel Cougar Canyon 2 board, so that SMP can be supported too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-04 02:04:21 +00:00
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <0>;
intel,apic-id = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <1>;
intel,apic-id = <1>;
};
cpu@2 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <2>;
intel,apic-id = <2>;
};
cpu@3 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <3>;
intel,apic-id = <3>;
};
};
x86: Add Intel Cougar Canyon 2 board This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-02-17 08:16:25 +00:00
microcode {
update@0 {
#include "microcode/m12306a2_00000008.dtsi"
};
update@1 {
#include "microcode/m12306a4_00000007.dtsi"
};
update@2 {
#include "microcode/m12306a5_00000007.dtsi"
};
update@3 {
#include "microcode/m12306a8_00000010.dtsi"
};
update@4 {
#include "microcode/m12306a9_0000001b.dtsi"
};
};
fsp {
compatible = "intel,ivybridge-fsp";
fsp,enable-ht;
};
pci {
#address-cells = <3>;
#size-cells = <2>;
compatible = "pci-x86";
u-boot,dm-pre-reloc;
ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,bd82x6x";
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
x86: cougarcanyon2: Add missing chipset interrupt information Add Panther Point chipset interrupt pin/PIRQ information, and enable the generation of PIRQ routing table and MP table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-12 08:26:47 +00:00
irq-router {
compatible = "intel,irq-router";
intel,pirq-config = "pci";
intel,actl-8bit;
intel,actl-addr = <0x44>;
intel,pirq-link = <0x60 8>;
intel,pirq-regmap = <
PIRQA 0
PIRQB 1
PIRQC 2
PIRQD 3
PIRQE 8
PIRQF 9
PIRQG 10
PIRQH 11
>;
intel,pirq-mask = <0xcee0>;
intel,pirq-routing = <
/* Panther Point PCI devices */
PCI_BDF(0, 2, 0) INTA PIRQA
PCI_BDF(0, 20, 0) INTA PIRQA
PCI_BDF(0, 22, 0) INTA PIRQA
PCI_BDF(0, 22, 1) INTB PIRQB
PCI_BDF(0, 22, 2) INTC PIRQC
PCI_BDF(0, 22, 3) INTD PIRQD
PCI_BDF(0, 25, 0) INTA PIRQA
PCI_BDF(0, 26, 0) INTA PIRQA
PCI_BDF(0, 27, 0) INTB PIRQA
PCI_BDF(0, 28, 0) INTA PIRQA
PCI_BDF(0, 28, 1) INTB PIRQB
PCI_BDF(0, 28, 2) INTC PIRQC
PCI_BDF(0, 28, 3) INTD PIRQD
PCI_BDF(0, 28, 4) INTA PIRQA
PCI_BDF(0, 28, 5) INTB PIRQB
PCI_BDF(0, 28, 6) INTC PIRQC
PCI_BDF(0, 28, 7) INTD PIRQD
PCI_BDF(0, 29, 0) INTA PIRQA
PCI_BDF(0, 31, 2) INTB PIRQB
PCI_BDF(0, 31, 3) INTC PIRQC
PCI_BDF(0, 31, 5) INTB PIRQB
PCI_BDF(0, 31, 6) INTC PIRQC
>;
};
x86: Add Intel Cougar Canyon 2 board This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-02-17 08:16:25 +00:00
spi0: spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
x86: cougarcanyon2: Update dts for SPI lock down It turns out that like Braswell, Intel FSP for IvyBridge requires SPI controller settings to be locked down, as the U-Boot ICH SPI driver fails with the following message on Cougar Canyon 2 board: "ICH SPI: Opcode 9f not found" Update the SPI node property to indicate this fact. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-04 02:04:16 +00:00
intel,spi-lock-down;
x86: Add Intel Cougar Canyon 2 board This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-02-17 08:16:25 +00:00
spi-flash@0 {
reg = <0>;
x86: dts: Add "m25p,fast-read" to SPI flash node Except ICH7 SPI, all SPI flashes connected to ICH9 / Fast SPI should have "m25p,fast-read" property present in their DT nodes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-29 12:18:23 +00:00
m25p,fast-read;
x86: dts: switch spi-flash to jedec, spi-nor compatible The x86 code and DT uses "spi-flash" to detect a flash node, switch to "jedec,spi-nor" in the DTS files and in fdtdec by switching the GENERIC_SPI_FLASH value to to jedec,spi-nor. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-02-10 10:16:21 +00:00
compatible = "winbond,w25q64bv", "jedec,spi-nor";
x86: Add Intel Cougar Canyon 2 board This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-02-17 08:16:25 +00:00
memory-map = <0xff800000 0x00800000>;
};
};
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x10>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x30 0x10>;
bank-name = "B";
};
gpioc {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x40 0x10>;
bank-name = "C";
};
};
};
};
Reference in a new issue Copy permalink