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u-boot/drivers/pci/fsl_pci_init.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
/*
fsl_pci: use 'Header Type' field to judge PCIE mode The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is EP or RC mode. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-21 23:35:42 +00:00
* Copyright 2007-2012 Freescale Semiconductor, Inc.
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
*/
fsl_pci_init cleanup. Do not enable normal errors created during probe (master abort, perr, and pcie Invalid Configuration access). Add CONFIG_PCI_NOSCAN board option to prevent bus scan. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2007-07-27 06:50:45 +00:00
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
#include <common.h>
env: Move env_get() to env.h Move env_get() over to the new header file. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-01 15:46:52 +00:00
#include <env.h>
common: Drop init.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:02 +00:00
#include <init.h>
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:05 +00:00
#include <log.h>
powerpc/fsl-pci: Add generic code to setup PCIe controllers Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-15 20:21:41 +00:00
#include <malloc.h>
#include <asm/fsl_serdes.h>
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
DECLARE_GLOBAL_DATA_PTR;
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
/*
* PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
*
* Initialize controller and call the common driver/pci pci_hose_scan to
* scan for bridges and devices.
*
* Hose fields which need to be pre-initialized by board specific code:
* regions[]
* first_busno
*
* Fields updated:
* last_busno
*/
#include <pci.h>
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
#include <asm/io.h>
fsl_pci: Renamed immap_fsl_pci.h to fsl_pci.h Rename the pci header for FSL HW so we can move some prototypes in there and stop doing explicit externs Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-04-02 18:22:48 +00:00
#include <asm/fsl_pci.h>
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS 0
#endif
#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
#define CONFIG_SYS_PCI_MEMORY_PHYS 0
#endif
#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
#endif
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
/* Setup one inbound ATMU window.
*
* We let the caller decide what the window size should be
*/
static void set_inbound_window(volatile pit_t *pi,
struct pci_region *r,
u64 size)
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
{
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
u32 sz = (__ilog2_u64(size) - 1);
fsl/pci: Add workaround for erratum A-005434 By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are mapped to 0xF, which is local memory. But for BSC9132, 0xF is CCSR, 0x0 is local memory. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-05-07 02:50:20 +00:00
#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
u32 flag = 0;
#else
u32 flag = PIWAR_LOCAL;
#endif
flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
out_be32(&pi->pitar, r->phys_start >> 12);
out_be32(&pi->piwbar, r->bus_start >> 12);
#ifdef CONFIG_SYS_PCI_64BIT
out_be32(&pi->piwbear, r->bus_start >> 44);
#else
out_be32(&pi->piwbear, 0);
#endif
if (r->flags & PCI_REGION_PREFETCH)
flag |= PIWAR_PF;
out_be32(&pi->piwar, flag | sz);
}
ppc/8xxx: Remove is_fsl_pci_agent All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent that uses the standard PCI programming model to determine host vs agent/end-point. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-04 19:00:55 +00:00
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
pci: Add ability to re-enumerate PCI buses Add a new 'pci enum' command which re-enumerates the PCI buses. This command is enabled via the CONFIG_CMD_PCI_ENUM define and can be useful in boards with FPGAs connected via PCI/PCIe, boards that support PCI hot-plugging, or during PCI debug. Also enable the 'pci enum' command for X-ES's Freescale-based boards. Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
2010-10-22 05:20:23 +00:00
/* Reset hose to make sure its in a clean state */
memset(hose, 0, sizeof(struct pci_controller));
ppc/8xxx: Remove is_fsl_pci_agent All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent that uses the standard PCI programming model to determine host vs agent/end-point. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-04 19:00:55 +00:00
pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
return fsl_is_pci_agent(hose);
}
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
u64 out_lo, u8 pcie_cap,
volatile pit_t *pi)
{
struct pci_region *r = hose->regions + hose->region_count;
u64 sz = min((u64)gd->ram_size, (1ull << 32));
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
pci_size_t pci_sz;
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
/* we have no space available for inbound memory mapping */
if (bus_start > out_lo) {
printf ("no space for inbound mapping of memory\n");
return 0;
}
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
/* limit size */
if ((bus_start + sz) > out_lo) {
sz = out_lo - bus_start;
debug ("limiting size to %llx\n", sz);
}
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
pci_sz = 1ull << __ilog2_u64(sz);
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
/*
* we can overlap inbound/outbound windows on PCI-E since RX & TX
* links a separate
*/
if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
(u64)bus_start, (u64)phys_start, (u64)sz);
pci_set_region(r, bus_start, phys_start, sz,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
PCI_REGION_PREFETCH);
/* if we aren't an exact power of two match, pci_sz is smaller
* round it up to the next power of two. We report the actual
* size to pci region tracking.
*/
if (pci_sz != sz)
sz = 2ull << __ilog2_u64(sz);
set_inbound_window(pi--, r++, sz);
sz = 0; /* make sure we dont set the R2 window */
} else {
debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
(u64)bus_start, (u64)phys_start, (u64)pci_sz);
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
pci_set_region(r, bus_start, phys_start, pci_sz,
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-06 15:49:31 +00:00
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
PCI_REGION_PREFETCH);
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
set_inbound_window(pi--, r++, pci_sz);
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
sz -= pci_sz;
bus_start += pci_sz;
phys_start += pci_sz;
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
pci_sz = 1ull << __ilog2_u64(sz);
if (sz) {
debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
(u64)bus_start, (u64)phys_start, (u64)pci_sz);
pci_set_region(r, bus_start, phys_start, pci_sz,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
PCI_REGION_PREFETCH);
set_inbound_window(pi--, r++, pci_sz);
sz -= pci_sz;
bus_start += pci_sz;
phys_start += pci_sz;
}
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
}
#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
powerpc: fix pci window initialization to work with > 4GB DRAM The existing code has a few errors that need to be fixed in order to support large RAM sizes. Fix those, and add a comment to make it clearer. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-27 21:09:42 +00:00
/*
* On 64-bit capable systems, set up a mapping for all of DRAM
* in high pci address space.
*/
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
pci_sz = 1ull << __ilog2_u64(gd->ram_size);
/* round up to the next largest power of two */
if (gd->ram_size > pci_sz)
powerpc: fix pci window initialization to work with > 4GB DRAM The existing code has a few errors that need to be fixed in order to support large RAM sizes. Fix those, and add a comment to make it clearer. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-27 21:09:42 +00:00
pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
powerpc: fix pci window initialization to work with > 4GB DRAM The existing code has a few errors that need to be fixed in order to support large RAM sizes. Fix those, and add a comment to make it clearer. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-27 21:09:42 +00:00
(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
(u64)CONFIG_SYS_PCI_MEMORY_PHYS,
(u64)pci_sz);
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
pci_set_region(r,
powerpc: fix pci window initialization to work with > 4GB DRAM The existing code has a few errors that need to be fixed in order to support large RAM sizes. Fix those, and add a comment to make it clearer. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-27 21:09:42 +00:00
CONFIG_SYS_PCI64_MEMORY_BUS,
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
CONFIG_SYS_PCI_MEMORY_PHYS,
pci_sz,
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-06 15:49:31 +00:00
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
PCI_REGION_PREFETCH);
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
set_inbound_window(pi--, r++, pci_sz);
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
#else
pci_sz = 1ull << __ilog2_u64(sz);
if (sz) {
debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
(u64)bus_start, (u64)phys_start, (u64)pci_sz);
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
pci_set_region(r, bus_start, phys_start, pci_sz,
pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarity The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-06 15:49:31 +00:00
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
PCI_REGION_PREFETCH);
sz -= pci_sz;
bus_start += pci_sz;
phys_start += pci_sz;
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
set_inbound_window(pi--, r++, pci_sz);
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
}
#endif
drivers/fsl_pci_init: Fix compile warning fsl_pci_init.c: In function 'fsl_pci_setup_inbound_windows': fsl_pci_init.c:122: warning: comparison is always true due to limited range of data type The check only makes sense if we are CONFIG_PHYS_64BIT Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-09 16:27:33 +00:00
#ifdef CONFIG_PHYS_64BIT
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
if (sz && (((u64)gd->ram_size) < (1ull << 32)))
printf("Was not able to map all of memory via "
"inbound windows -- %lld remaining\n", sz);
drivers/fsl_pci_init: Fix compile warning fsl_pci_init.c: In function 'fsl_pci_setup_inbound_windows': fsl_pci_init.c:122: warning: comparison is always true due to limited range of data type The check only makes sense if we are CONFIG_PHYS_64BIT Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-09 16:27:33 +00:00
#endif
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
hose->region_count = r - hose->regions;
return 1;
pci/fsl_pci_init: Add a common PCI inbound setup function Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-22 19:06:24 +00:00
}
powerpc/boot: Change the macro of Boot from SRIO and PCIE master module Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-07 08:30:46 +00:00
#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
powerpc/corenet_ds: Master module for boot from PCIE For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:02 +00:00
static void fsl_pcie_boot_master(pit_t *pi)
{
/* configure inbound window for slave's u-boot image */
debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
struct pci_region r_inbound;
u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
- 1;
pci_set_region(&r_inbound,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
sz_inbound,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
set_inbound_window(pi--, &r_inbound,
CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
/* configure inbound window for slave's u-boot image */
debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
pci_set_region(&r_inbound,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
sz_inbound,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
set_inbound_window(pi--, &r_inbound,
CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
/* configure inbound window for slave's ucode and ENV */
debug("PCIEBOOT - MASTER: Inbound window for slave's "
"ucode and ENV; "
"Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
- 1;
pci_set_region(&r_inbound,
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
sz_inbound,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
set_inbound_window(pi--, &r_inbound,
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
}
static void fsl_pcie_boot_master_release_slave(int port)
{
unsigned long release_addr;
/* now release slave's core 0 */
switch (port) {
case 1:
release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
break;
driver/pci: Fix compiling error Fix compiling error in case CONFIG_SYS_PCIE2_MEM_VIRT or CONFIG_SYS_PCIE3_MEM_VIRT not defined. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:04 +00:00
#ifdef CONFIG_SYS_PCIE2_MEM_VIRT
powerpc/corenet_ds: Master module for boot from PCIE For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:02 +00:00
case 2:
release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
break;
driver/pci: Fix compiling error Fix compiling error in case CONFIG_SYS_PCIE2_MEM_VIRT or CONFIG_SYS_PCIE3_MEM_VIRT not defined. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:04 +00:00
#endif
#ifdef CONFIG_SYS_PCIE3_MEM_VIRT
powerpc/corenet_ds: Master module for boot from PCIE For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:02 +00:00
case 3:
release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
break;
driver/pci: Fix compiling error Fix compiling error in case CONFIG_SYS_PCIE2_MEM_VIRT or CONFIG_SYS_PCIE3_MEM_VIRT not defined. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:04 +00:00
#endif
powerpc/corenet_ds: Master module for boot from PCIE For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:02 +00:00
default:
release_addr = 0;
break;
}
if (release_addr != 0) {
out_be32((void *)release_addr,
CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
debug("PCIEBOOT - MASTER: "
"Release slave successfully! Now the slave should start up!\n");
} else {
debug("PCIEBOOT - MASTER: "
"Release slave failed!\n");
}
}
#endif
fsl_pci: Update PCIe boot ouput This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-28 23:47:25 +00:00
void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
{
fsl_pci: Update PCIe boot ouput This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-28 23:47:25 +00:00
u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
u16 temp16;
u32 temp32;
fsl_pci: Add support for FSL PCIe controllers v2.x FSL PCIe controller v2.1: - New MSI inbound window - Same Inbound windows address as PCIe controller v1.x Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window FSL PCIe controller v2.2 and v2.3: - Different addresses for PCIe inbound window 3,2,1 - Exposed PCIe inbound window 0 - New PCIe interrupt status register Added new Interrupt Status register to struct ccsr_pci & updated pit_t array size to reflect the 4 inbound windows. To maintain backward compatiblilty, on V2.2 or greater controllers we start with inbound window 1 and leave inbound 0 with its default value (which maps to CCSRBAR). Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-04 03:30:43 +00:00
u32 block_rev;
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:49:27 +00:00
int enabled, r, inbound = 0;
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
u16 ltssm;
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:49:27 +00:00
u8 temp8, pcie_cap;
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
int pcie_cap_pos;
int pci_dcr;
int pci_dsr;
int pci_lsr;
#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
int pci_lcr;
#endif
pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_init Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-04 01:44:55 +00:00
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_init Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-04 02:02:02 +00:00
struct pci_region *reg = hose->regions + hose->region_count;
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:49:27 +00:00
pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
/* Initialize ATMU registers based on hose regions and flags */
Code cleanup: fix old style assignment ambiguities like "=-" etc. Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-07-14 13:19:07 +00:00
volatile pot_t *po = &pci->pot[1]; /* skip 0 */
fsl_pci: Add support for FSL PCIe controllers v2.x FSL PCIe controller v2.1: - New MSI inbound window - Same Inbound windows address as PCIe controller v1.x Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window FSL PCIe controller v2.2 and v2.3: - Different addresses for PCIe inbound window 3,2,1 - Exposed PCIe inbound window 0 - New PCIe interrupt status register Added new Interrupt Status register to struct ccsr_pci & updated pit_t array size to reflect the 4 inbound windows. To maintain backward compatiblilty, on V2.2 or greater controllers we start with inbound window 1 and leave inbound 0 with its default value (which maps to CCSRBAR). Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-04 03:30:43 +00:00
volatile pit_t *pi;
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
u64 out_hi = 0, out_lo = -1ULL;
u32 pcicsrbar, pcicsrbar_sz;
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_init Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-04 01:44:55 +00:00
pci_setup_indirect(hose, cfg_addr, cfg_data);
FSL PCI: Configure PCIe reference ratio Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured. This adds PEX_CCB_DIV #define which can be defined for each type of CPU/platform. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-12 17:56:41 +00:00
#ifdef PEX_CCB_DIV
/* Configure the PCIE controller core clock ratio */
pci_hose_write_config_dword(hose, dev, 0x440,
((gd->bus_clk / 1000000) *
(16 / PEX_CCB_DIV)) / 333);
#endif
fsl_pci: Add support for FSL PCIe controllers v2.x FSL PCIe controller v2.1: - New MSI inbound window - Same Inbound windows address as PCIe controller v1.x Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window FSL PCIe controller v2.2 and v2.3: - Different addresses for PCIe inbound window 3,2,1 - Exposed PCIe inbound window 0 - New PCIe interrupt status register Added new Interrupt Status register to struct ccsr_pci & updated pit_t array size to reflect the 4 inbound windows. To maintain backward compatiblilty, on V2.2 or greater controllers we start with inbound window 1 and leave inbound 0 with its default value (which maps to CCSRBAR). Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-04 03:30:43 +00:00
block_rev = in_be32(&pci->block_rev1);
if (PEX_IP_BLK_REV_2_2 <= block_rev) {
pi = &pci->pit[2]; /* 0xDC0 */
} else {
pi = &pci->pit[3]; /* 0xDE0 */
}
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
/* Handle setup of outbound windows first */
for (r = 0; r < hose->region_count; r++) {
unsigned long flags = hose->regions[r].flags;
u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_init Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-04 02:02:02 +00:00
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
if (flags != PCI_REGION_SYS_MEMORY) {
u64 start = hose->regions[r].bus_start;
u64 end = start + hose->regions[r].size;
pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_init Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-04 02:02:02 +00:00
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
out_be32(&po->potar, start >> 12);
pci/fsl_pci_init: Enable larger address and setting inbound windows properly * PCI Inbound window was setup incorrectly. The PCI address and system address were swapped. The PCI address should be setting piwar/piwbear and the system address should be setting pitar. * Removed masking of addresses to allow for system address to support system address & PCI address >32-bits * Set PIWBEAR & POTEAR to allow for full 64-bit PCI addresses * Respect the PCI_REGION_PREFETCH for inbound windows Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-21 15:13:14 +00:00
#ifdef CONFIG_SYS_PCI_64BIT
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
out_be32(&po->potear, start >> 44);
pci/fsl_pci_init: Enable larger address and setting inbound windows properly * PCI Inbound window was setup incorrectly. The PCI address and system address were swapped. The PCI address should be setting piwar/piwbear and the system address should be setting pitar. * Removed masking of addresses to allow for system address to support system address & PCI address >32-bits * Set PIWBEAR & POTEAR to allow for full 64-bit PCI addresses * Respect the PCI_REGION_PREFETCH for inbound windows Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-21 15:13:14 +00:00
#else
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
out_be32(&po->potear, 0);
pci/fsl_pci_init: Enable larger address and setting inbound windows properly * PCI Inbound window was setup incorrectly. The PCI address and system address were swapped. The PCI address should be setting piwar/piwbear and the system address should be setting pitar. * Removed masking of addresses to allow for system address to support system address & PCI address >32-bits * Set PIWBEAR & POTEAR to allow for full 64-bit PCI addresses * Respect the PCI_REGION_PREFETCH for inbound windows Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-21 15:13:14 +00:00
#endif
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
if (hose->regions[r].flags & PCI_REGION_IO) {
out_be32(&po->powar, POWAR_EN | sz |
POWAR_IO_READ | POWAR_IO_WRITE);
} else {
out_be32(&po->powar, POWAR_EN | sz |
POWAR_MEM_READ | POWAR_MEM_WRITE);
out_lo = min(start, out_lo);
out_hi = max(end, out_hi);
}
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
po++;
}
}
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
/* setup PCSRBAR/PEXCSRBAR */
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
pcicsrbar_sz = ~pcicsrbar_sz + 1;
if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
(out_lo > 0x100000000ull))
pcicsrbar = 0x100000000ull - pcicsrbar_sz;
else
pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
out_lo = min(out_lo, (u64)pcicsrbar);
debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
hose->region_count++;
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:49:27 +00:00
/* see if we are a PCIe or PCI controller */
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
pci_dcr = pcie_cap_pos + 0x08;
pci_dsr = pcie_cap_pos + 0x0a;
pci_lsr = pcie_cap_pos + 0x12;
pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:49:27 +00:00
powerpc/boot: Change the macro of Boot from SRIO and PCIE master module Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-07 08:30:46 +00:00
#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
powerpc/corenet_ds: Master module for boot from PCIE For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:02 +00:00
/* boot from PCIE --master */
env: Rename getenv/_f() to env_get() We are now using an env_ prefix for environment functions. Rename these two functions for consistency. Also add function comments in common.h. Quite a few places use getenv() in a condition context, provoking a warning from checkpatch. These are fixed up in this patch also. Suggested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-03 18:22:12 +00:00
char *s = env_get("bootmaster");
powerpc/corenet_ds: Master module for boot from PCIE For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:02 +00:00
char pcie[6];
sprintf(pcie, "PCIE%d", pci_info->pci_num);
if (s && (strcmp(s, pcie) == 0)) {
debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
pci_info->pci_num);
fsl_pcie_boot_master((pit_t *)pi);
} else {
/* inbound */
inbound = fsl_pci_setup_inbound_windows(hose,
out_lo, pcie_cap, pi);
}
#else
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
/* inbound */
inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
powerpc/corenet_ds: Master module for boot from PCIE For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:02 +00:00
#endif
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
for (r = 0; r < hose->region_count; r++)
GCC4.6: Squash warnings in fsl_pci_init.c fsl_pci_init.c: In function 'fsl_pci_init': fsl_pci_init.c:308: warning: format '%08x' expects type 'unsigned int', but argument 6 has type 'long unsigned int' fsl_pci_init.c:347: warning: format '%x' expects type 'unsigned int', but argument 2 has type 'volatile u32 *' fsl_pci_init.c: In function 'fsl_pci_init': fsl_pci_init.c:308: warning: format '%016llx' expects type 'long long unsigned int', but argument 4 has type 'pci_addr_t' fsl_pci_init.c:308: warning: format '%016llx' expects type 'long long unsigned int', but argument 5 has type 'pci_size_t' fsl_pci_init.c:308: warning: format '%08x' expects type 'unsigned int', but argument 6 has type 'long unsigned int' Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-21 14:17:21 +00:00
debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
(u64)hose->regions[r].phys_start,
GCC4.6: Squash warnings in fsl_pci_init.c fsl_pci_init.c: In function 'fsl_pci_init': fsl_pci_init.c:308: warning: format '%08x' expects type 'unsigned int', but argument 6 has type 'long unsigned int' fsl_pci_init.c:347: warning: format '%x' expects type 'unsigned int', but argument 2 has type 'volatile u32 *' fsl_pci_init.c: In function 'fsl_pci_init': fsl_pci_init.c:308: warning: format '%016llx' expects type 'long long unsigned int', but argument 4 has type 'pci_addr_t' fsl_pci_init.c:308: warning: format '%016llx' expects type 'long long unsigned int', but argument 5 has type 'pci_size_t' fsl_pci_init.c:308: warning: format '%08x' expects type 'unsigned int', but argument 6 has type 'long unsigned int' Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-21 14:17:21 +00:00
(u64)hose->regions[r].bus_start,
(u64)hose->regions[r].size,
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
hose->regions[r].flags);
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
pci_register_hose(hose);
pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
hose->current_busno = hose->first_busno;
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
cleanup: Fix typos and misspellings in various files. Recieve/Receive recieve/receive Interupt/Interrupt interupt/interrupt Addres/Address addres/address Signed-off-by: Mike Williams <mike@mikebwilliams.com>
2011-07-22 04:01:30 +00:00
out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except
fsl_pci_init cleanup. Do not enable normal errors created during probe (master abort, perr, and pcie Invalid Configuration access). Add CONFIG_PCI_NOSCAN board option to prevent bus scan. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2007-07-27 06:50:45 +00:00
* - Master abort (pci)
* - Master PERR (pci)
* - ICCA (PCIe)
*/
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32);
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-01 15:55:58 +00:00
#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
pci_lcr = pcie_cap_pos + 0x10;
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-01 15:55:58 +00:00
temp32 = 0;
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-01 15:55:58 +00:00
temp32 &= ~0x03; /* Disable ASPM */
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-02-01 15:55:58 +00:00
udelay(1);
#endif
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:49:27 +00:00
if (pcie_cap == PCI_CAP_ID_EXP) {
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2013-07-03 23:25:03 +00:00
if (block_rev >= PEX_IP_BLK_REV_3_0) {
#define PEX_CSR0_LTSSM_MASK 0xFC
#define PEX_CSR0_LTSSM_SHIFT 2
ltssm = (in_be32(&pci->pex_csr0)
& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
enabled = (ltssm == 0x11) ? 1 : 0;
T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15. Soft reset PCIe can fix this issue. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-26 08:13:09 +00:00
#ifdef CONFIG_FSL_PCIE_RESET
int i;
/* assert PCIe reset */
setbits_be32(&pci->pdb_stat, 0x08000000);
(void) in_be32(&pci->pdb_stat);
udelay(1000);
/* clear PCIe reset */
clrbits_be32(&pci->pdb_stat, 0x08000000);
asm("sync;isync");
for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
pci_hose_read_config_word(hose, dev, PCI_LTSSM,
&ltssm);
udelay(1000);
}
#endif
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2013-07-03 23:25:03 +00:00
} else {
/* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */
/* enabled = ltssm >= PCI_LTSSM_L0; */
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
enabled = ltssm >= PCI_LTSSM_L0;
Handle MPC85xx PCIe reset errata (PCI-Ex 38) On the MPC85xx boards that have PCIe enable the PCIe errata fix. (MPC8544DS, MPC8548CDS, MPC8568MDS). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-07 18:17:34 +00:00
#ifdef CONFIG_FSL_PCIE_RESET
if (ltssm == 1) {
int i;
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
/* assert PCIe reset */
setbits_be32(&pci->pdb_stat, 0x08000000);
(void) in_be32(&pci->pdb_stat);
Handle MPC85xx PCIe reset errata (PCI-Ex 38) On the MPC85xx boards that have PCIe enable the PCIe errata fix. (MPC8544DS, MPC8548CDS, MPC8568MDS). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-07 18:17:34 +00:00
udelay(100);
GCC4.6: Squash warnings in fsl_pci_init.c fsl_pci_init.c: In function 'fsl_pci_init': fsl_pci_init.c:308: warning: format '%08x' expects type 'unsigned int', but argument 6 has type 'long unsigned int' fsl_pci_init.c:347: warning: format '%x' expects type 'unsigned int', but argument 2 has type 'volatile u32 *' fsl_pci_init.c: In function 'fsl_pci_init': fsl_pci_init.c:308: warning: format '%016llx' expects type 'long long unsigned int', but argument 4 has type 'pci_addr_t' fsl_pci_init.c:308: warning: format '%016llx' expects type 'long long unsigned int', but argument 5 has type 'pci_size_t' fsl_pci_init.c:308: warning: format '%08x' expects type 'unsigned int', but argument 6 has type 'long unsigned int' Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org>
2011-10-21 14:17:21 +00:00
debug(" Asserting PCIe reset @%p = %x\n",
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
&pci->pdb_stat, in_be32(&pci->pdb_stat));
/* clear PCIe reset */
clrbits_be32(&pci->pdb_stat, 0x08000000);
Handle MPC85xx PCIe reset errata (PCI-Ex 38) On the MPC85xx boards that have PCIe enable the PCIe errata fix. (MPC8544DS, MPC8548CDS, MPC8568MDS). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-07 18:17:34 +00:00
asm("sync;isync");
for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
pci_hose_read_config_word(hose, dev, PCI_LTSSM,
&ltssm);
udelay(1000);
debug("....PCIe link error. "
"LTSSM=0x%02x.\n", ltssm);
}
enabled = ltssm >= PCI_LTSSM_L0;
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
/* we need to re-write the bar0 since a reset will
* clear it
*/
pci_hose_write_config_dword(hose, dev,
PCI_BASE_ADDRESS_0, pcicsrbar);
Handle MPC85xx PCIe reset errata (PCI-Ex 38) On the MPC85xx boards that have PCIe enable the PCIe errata fix. (MPC8544DS, MPC8548CDS, MPC8568MDS). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-07 18:17:34 +00:00
}
#endif
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2013-07-03 23:25:03 +00:00
}
Handle MPC85xx PCIe reset errata (PCI-Ex 38) On the MPC85xx boards that have PCIe enable the PCIe errata fix. (MPC8544DS, MPC8548CDS, MPC8568MDS). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-07 18:17:34 +00:00
powerpc/p4080ds: fix PCI-e x8 link training down failure Due to SerDes configuration error, if we set the PCI-e controller link width as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to PCI-e slot, it fails to train down to the PCI-e device's link width. According to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between RC and EP. Signed-off-by: Yuanquan Chen <B41889@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-26 23:49:45 +00:00
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
if (enabled == 0) {
serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
temp32 = in_be32(&srds_regs->srdspccr0);
if ((temp32 >> 28) == 3) {
int i;
out_be32(&srds_regs->srdspccr0, 2 << 28);
setbits_be32(&pci->pdb_stat, 0x08000000);
in_be32(&pci->pdb_stat);
udelay(100);
clrbits_be32(&pci->pdb_stat, 0x08000000);
asm("sync;isync");
for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
udelay(1000);
}
enabled = ltssm >= PCI_LTSSM_L0;
}
}
#endif
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
if (!enabled) {
fsl/pcie: Change 'no link' to 'undetermined' for pcie endpoint Even u-boot boots up, the pcie link may not setup correctly when Freescale SOC acts as endpoint. So change the link status from 'no link' to 'undetermined' to reduce the confusion. The link status can check from host side eventually. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-12 19:49:23 +00:00
/* Let the user know there's no PCIe link for root
* complex. for endpoint, the link may not setup, so
* print undetermined.
*/
if (fsl_is_pci_agent(hose))
printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
else
printf("no link, regs @ 0x%lx\n", pci_info->regs);
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
hose->last_busno = hose->first_busno;
return;
}
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
out_be32(&pci->pme_msg_det, 0xffffffff);
out_be32(&pci->pme_msg_int_en, 0xffffffff);
fsl_pci: Update PCIe boot ouput This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-28 23:47:25 +00:00
/* Print the negotiated PCIe link width */
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
driver/fsl_pci:Update print to display PCIe generation Current print only display width of PCIe device. Add print to display PCIe generation supported by the device. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-01-25 07:23:32 +00:00
printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
(temp16 & 0xf), pci_info->regs);
fsl_pci: Update PCIe boot ouput This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-28 23:47:25 +00:00
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
hose->current_busno++; /* Start scan with secondary */
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
}
mpc85xx: pcie: Implement workaround for Erratum A007815 The read-only-write-enable bit is set by default and must be cleared to prevent overwriting read-only registers. This should be done immediately after resetting the PCI Express controller. Reviewed-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz> [York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-01 20:22:34 +00:00
#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
/* The Read-Only Write Enable bit defaults to 1 instead of 0.
* Set to 0 to protect the read-only registers.
*/
clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
#endif
fsl_pci_init - Remove self PCSRBAR allocation CPU physical address space was being wasted by allocating a PCSRBAR PCI inbound region to it's memory space. As a rule, PCSRBAR should be left alone since it does not affect transactions from self and other masters may have changed it. Signed-off-by: Ed Swarthout <ed.swarthout@freescale.com>
2007-08-21 04:55:33 +00:00
/* Use generic setup_device to initialize standard pci regs,
* but do not allocate any windows since any BAR found (such
* as PCSRBAR) is not in this cpu's memory space.
*/
pciauto_setup_device(hose, dev, 0, hose->pci_mem,
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
hose->pci_prefetch, hose->pci_io);
fsl_pci_init - Remove self PCSRBAR allocation CPU physical address space was being wasted by allocating a PCSRBAR PCI inbound region to it's memory space. As a rule, PCSRBAR should be left alone since it does not affect transactions from self and other masters may have changed it. Signed-off-by: Ed Swarthout <ed.swarthout@freescale.com>
2007-08-21 04:55:33 +00:00
fsl_pci_init enable COMMAND_MEMORY if inbound window Patch 16e23c3f removed PCSRBAR allocation. But passing zero windows to pciauto_setup_device has the side effect of not getting COMMAND_MEMORY set. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2007-10-19 22:51:40 +00:00
if (inbound) {
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
pci_hose_write_config_word(hose, dev, PCI_COMMAND,
temp16 | PCI_COMMAND_MEMORY);
}
fsl_pci_init cleanup. Do not enable normal errors created during probe (master abort, perr, and pcie Invalid Configuration access). Add CONFIG_PCI_NOSCAN board option to prevent bus scan. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2007-07-27 06:50:45 +00:00
#ifndef CONFIG_PCI_NOSCAN
fsl_pci: use 'Header Type' field to judge PCIE mode The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is EP or RC mode. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-21 23:35:42 +00:00
if (!fsl_is_pci_agent(hose)) {
fsl_pci_init: Quiet scanning printf() The "Scanning PCI bus X" message doesn't provide any real useful information, so remove it. Original output: PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Updated output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: galak@kernel.crashing.org
2010-10-29 22:59:26 +00:00
debug(" Scanning PCI bus %02x\n",
fsl_pci_init do not scan bus when configured as an end-point Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2008-10-09 04:38:00 +00:00
hose->current_busno);
hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
} else {
fsl: Clean up printing of PCI boot info Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like: ... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
2010-10-29 22:59:24 +00:00
debug(" Not scanning PCI bus %02x. PI=%x\n",
fsl_pci_init do not scan bus when configured as an end-point Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2008-10-09 04:38:00 +00:00
hose->current_busno, temp8);
hose->last_busno = hose->current_busno;
}
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:49:27 +00:00
/* if we are PCIe - update limit regs and subordinate busno
* for the virtual P2P bridge
*/
if (pcie_cap == PCI_CAP_ID_EXP) {
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
}
fsl_pci_init cleanup. Do not enable normal errors created during probe (master abort, perr, and pcie Invalid Configuration access). Add CONFIG_PCI_NOSCAN board option to prevent bus scan. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2007-07-27 06:50:45 +00:00
#else
hose->last_busno = hose->current_busno;
#endif
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
/* Clear all error indications */
pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIe Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:49:27 +00:00
if (pcie_cap == PCI_CAP_ID_EXP)
pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memory The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-05 12:59:35 +00:00
out_be32(&pci->pme_msg_det, 0xffffffff);
out_be32(&pci->pedr, 0xffffffff);
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
pci_hose_read_config_word(hose, dev, pci_dsr, &temp16);
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
if (temp16) {
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff);
Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Zhang Wei <wei.zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-02 19:09:49 +00:00
}
pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
if (temp16) {
pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
}
}
pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-ranges Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-23 05:01:06 +00:00
fsl_pci_init_port end-point initialization is broken commit 70ed869e broke fsl pcie end-point initialization. Returning 0 is not correct. The function must return the first free bus number for the next controller. fsl_pci_init() must still be called and a bus allocated even if the controller is an end-point. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-02 15:05:49 +00:00
int fsl_is_pci_agent(struct pci_controller *hose)
{
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
int pcie_cap_pos;
fsl_pci: use 'Header Type' field to judge PCIE mode The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is EP or RC mode. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-21 23:35:42 +00:00
u8 pcie_cap;
fsl_pci_init_port end-point initialization is broken commit 70ed869e broke fsl pcie end-point initialization. Returning 0 is not correct. The function must return the first free bus number for the next controller. fsl_pci_init() must still be called and a bus allocated even if the controller is an end-point. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-02 15:05:49 +00:00
pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
fsl_pci: use 'Header Type' field to judge PCIE mode The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is EP or RC mode. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-21 23:35:42 +00:00
if (pcie_cap == PCI_CAP_ID_EXP) {
u8 header_type;
pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE,
&header_type);
return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
} else {
u8 prog_if;
fsl_pci_init_port end-point initialization is broken commit 70ed869e broke fsl pcie end-point initialization. Returning 0 is not correct. The function must return the first free bus number for the next controller. fsl_pci_init() must still be called and a bus allocated even if the controller is an end-point. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-02 15:05:49 +00:00
fsl_pci: use 'Header Type' field to judge PCIE mode The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is EP or RC mode. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-21 23:35:42 +00:00
pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
powerpc/pcie: add PCIe version 3.x support T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2013-07-03 23:25:03 +00:00
/* Programming Interface (PCI_CLASS_PROG)
* 0 == pci host or pcie root-complex,
* 1 == pci agent or pcie end-point
*/
fsl_pci: use 'Header Type' field to judge PCIE mode The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is EP or RC mode. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-21 23:35:42 +00:00
return (prog_if == FSL_PROG_IF_AGENT);
}
fsl_pci_init_port end-point initialization is broken commit 70ed869e broke fsl pcie end-point initialization. Returning 0 is not correct. The function must return the first free bus number for the next controller. fsl_pci_init() must still be called and a bus allocated even if the controller is an end-point. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-02 15:05:49 +00:00
}
driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controller fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-21 01:59:42 +00:00
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
Revert "ppc/85xx/pci: fsl_pci_init: pcie agent mode support" This reverts commit 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc. There isn't any need to modify the API for fsl_pci_init_port to pass the status of host/agent(end-point) status. We can determine that internally to fsl_pci_init_port. Revert the patch that makes the API change. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-04 07:29:04 +00:00
struct pci_controller *hose, int busno)
driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controller fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-21 01:59:42 +00:00
{
volatile ccsr_fsl_pci_t *pci;
struct pci_region *r;
fsl_pci_init: Make fsl_pci_init_port() PCI/PCIe aware Previously fsl_pci_init_port() always assumed that a port was a PCIe port and would incorrectly print messages for a PCI port such as the following on bootup: PCI1: 32 bit, 33 MHz, sync, host, arbiter Scanning PCI bus 00 PCIE1 on bus 00 - 00 This change corrects the output of fsl_pci_init_port(): PCI1: 32 bit, 33 MHz, sync, host, arbiter Scanning PCI bus 00 PCI1 on bus 00 - 00 Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-10-28 20:24:59 +00:00
pci_dev_t dev = PCI_BDF(busno,0,0);
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
int pcie_cap_pos;
fsl_pci_init: Make fsl_pci_init_port() PCI/PCIe aware Previously fsl_pci_init_port() always assumed that a port was a PCIe port and would incorrectly print messages for a PCI port such as the following on bootup: PCI1: 32 bit, 33 MHz, sync, host, arbiter Scanning PCI bus 00 PCIE1 on bus 00 - 00 This change corrects the output of fsl_pci_init_port(): PCI1: 32 bit, 33 MHz, sync, host, arbiter Scanning PCI bus 00 PCI1 on bus 00 - 00 Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-10-28 20:24:59 +00:00
u8 pcie_cap;
driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controller fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-21 01:59:42 +00:00
pci = (ccsr_fsl_pci_t *) pci_info->regs;
/* on non-PCIe controllers we don't have pme_msg_det so this code
* should do nothing since the read will return 0
*/
if (in_be32(&pci->pme_msg_det)) {
out_be32(&pci->pme_msg_det, 0xffffffff);
debug (" with errors. Clearing. Now 0x%08x",
pci->pme_msg_det);
}
r = hose->regions + hose->region_count;
/* outbound memory */
pci_set_region(r++,
pci_info->mem_bus,
pci_info->mem_phys,
pci_info->mem_size,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
pci_info->io_bus,
pci_info->io_phys,
pci_info->io_size,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = busno;
fsl_pci: Update PCIe boot ouput This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-28 23:47:25 +00:00
fsl_pci_init(hose, pci_info);
driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controller fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-21 01:59:42 +00:00
fsl_pci_init_port end-point initialization is broken commit 70ed869e broke fsl pcie end-point initialization. Returning 0 is not correct. The function must return the first free bus number for the next controller. fsl_pci_init() must still be called and a bus allocated even if the controller is an end-point. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-02 15:05:49 +00:00
if (fsl_is_pci_agent(hose)) {
fsl_pci_config_unlock(hose);
hose->last_busno = hose->first_busno;
powerpc/boot: Change the macro of Boot from SRIO and PCIE master module Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-07 08:30:46 +00:00
#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
powerpc/corenet_ds: Master module for boot from PCIE For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:02 +00:00
} else {
/* boot from PCIE --master releases slave's core 0 */
env: Rename getenv/_f() to env_get() We are now using an env_ prefix for environment functions. Rename these two functions for consistency. Also add function comments in common.h. Quite a few places use getenv() in a condition context, provoking a warning from checkpatch. These are fixed up in this patch also. Suggested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-03 18:22:12 +00:00
char *s = env_get("bootmaster");
powerpc/corenet_ds: Master module for boot from PCIE For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:02 +00:00
char pcie[6];
sprintf(pcie, "PCIE%d", pci_info->pci_num);
if (s && (strcmp(s, pcie) == 0))
fsl_pcie_boot_master_release_slave(pci_info->pci_num);
#endif
fsl_pci_init_port end-point initialization is broken commit 70ed869e broke fsl pcie end-point initialization. Returning 0 is not correct. The function must return the first free bus number for the next controller. fsl_pci_init() must still be called and a bus allocated even if the controller is an end-point. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-02 15:05:49 +00:00
}
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
fsl: Clean up printing of PCI boot info Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like: ... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
2010-10-29 22:59:24 +00:00
printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
fsl_pci: Update PCIe boot ouput This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-28 23:47:25 +00:00
"e" : "", pci_info->pci_num,
fsl: Clean up printing of PCI boot info Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like: ... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
2010-10-29 22:59:24 +00:00
hose->first_busno, hose->last_busno);
driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controller fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-21 01:59:42 +00:00
return(hose->last_busno + 1);
}
pci/fsl_pci_init: Enable inbound PCI config cycles Add fsl_pci_config_unlock() function to enable a PCI/PCIe interface configured in agent/endpoint mode to respond to inbound PCI configuration cycles. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-10-29 17:39:26 +00:00
/* Enable inbound PCI config cycles for agent/endpoint interface */
void fsl_pci_config_unlock(struct pci_controller *hose)
{
pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
int pcie_cap_pos;
pci/fsl_pci_init: Enable inbound PCI config cycles Add fsl_pci_config_unlock() function to enable a PCI/PCIe interface configured in agent/endpoint mode to respond to inbound PCI configuration cycles. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-10-29 17:39:26 +00:00
u8 pcie_cap;
u16 pbfr;
fsl_pci: use 'Header Type' field to judge PCIE mode The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is EP or RC mode. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-21 23:35:42 +00:00
if (!fsl_is_pci_agent(hose))
pci/fsl_pci_init: Enable inbound PCI config cycles Add fsl_pci_config_unlock() function to enable a PCI/PCIe interface configured in agent/endpoint mode to respond to inbound PCI configuration cycles. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-10-29 17:39:26 +00:00
return;
PCIe:change the method to get the address of a requested capability in configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-12 05:46:33 +00:00
pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
pci/fsl_pci_init: Enable inbound PCI config cycles Add fsl_pci_config_unlock() function to enable a PCI/PCIe interface configured in agent/endpoint mode to respond to inbound PCI configuration cycles. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-10-29 17:39:26 +00:00
if (pcie_cap != 0x0) {
fsl/pci: Set CFG_READY for PCIe v3.0 and later Freescale PCIe controllers v3.0 and later need to set bit CFG_READY to allow all inbound configuration transactions to be processed normally when in EP mode. However, bit CFG_READY has been moved from PCIe configuration space to CCSR PCIe configuration register comparing previous version. The patch is to set this bit according to PCIe version. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-27 05:24:39 +00:00
ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
u32 block_rev = in_be32(&pci->block_rev1);
pci/fsl_pci_init: Enable inbound PCI config cycles Add fsl_pci_config_unlock() function to enable a PCI/PCIe interface configured in agent/endpoint mode to respond to inbound PCI configuration cycles. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-10-29 17:39:26 +00:00
/* PCIe - set CFG_READY bit of Configuration Ready Register */
fsl/pci: Set CFG_READY for PCIe v3.0 and later Freescale PCIe controllers v3.0 and later need to set bit CFG_READY to allow all inbound configuration transactions to be processed normally when in EP mode. However, bit CFG_READY has been moved from PCIe configuration space to CCSR PCIe configuration register comparing previous version. The patch is to set this bit according to PCIe version. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-27 05:24:39 +00:00
if (block_rev >= PEX_IP_BLK_REV_3_0)
setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
else
pci_hose_write_config_byte(hose, dev,
FSL_PCIE_CFG_RDY, 0x1);
pci/fsl_pci_init: Enable inbound PCI config cycles Add fsl_pci_config_unlock() function to enable a PCI/PCIe interface configured in agent/endpoint mode to respond to inbound PCI configuration cycles. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-10-29 17:39:26 +00:00
} else {
/* PCI - clear ACL bit of PBFR */
pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
pbfr &= ~0x20;
pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
}
}
powerpc/fsl-pci: Add generic code to setup PCIe controllers Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-15 20:21:41 +00:00
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
Minor Coding Style Cleanup. Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-02-02 21:36:10 +00:00
defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
powerpc/fsl-pci: Add generic code to setup PCIe controllers Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-15 20:21:41 +00:00
int fsl_configure_pcie(struct fsl_pci_info *info,
struct pci_controller *hose,
const char *connected, int busno)
{
int is_endpoint;
set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
fsl_pci: Update PCIe boot ouput This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-28 23:47:25 +00:00
powerpc/fsl-pci: Add generic code to setup PCIe controllers Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-15 20:21:41 +00:00
is_endpoint = fsl_setup_hose(hose, info->regs);
fsl_pci: Update PCIe boot ouput This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-28 23:47:25 +00:00
printf("PCIe%u: %s", info->pci_num,
is_endpoint ? "Endpoint" : "Root Complex");
if (connected)
printf(" of %s", connected);
puts(", ");
powerpc/fsl-pci: Add generic code to setup PCIe controllers Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-15 20:21:41 +00:00
return fsl_pci_init_port(info, hose, busno);
}
#if defined(CONFIG_FSL_CORENET)
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:19 +00:00
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
#define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
#define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
#define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
#else
powerpc/fsl-pci: Add generic code to setup PCIe controllers Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-15 20:21:41 +00:00
#define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
#define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
#define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
#define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:19 +00:00
#endif
powerpc/fsl-pci: Add generic code to setup PCIe controllers Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-15 20:21:41 +00:00
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC85xx)
#define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
#define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
#define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
#define _DEVDISR_PCIE4 0
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC86xx)
#define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
#define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
#define _DEVDISR_PCIE3 0
#define _DEVDISR_PCIE4 0
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
(&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
#else
#error "No defines for DEVDISR_PCIE"
#endif
/* Implement a dummy function for those platforms w/o SERDES */
static const char *__board_serdes_name(enum srds_prtcl device)
{
switch (device) {
#ifdef CONFIG_SYS_PCIE1_NAME
case PCIE1:
return CONFIG_SYS_PCIE1_NAME;
#endif
#ifdef CONFIG_SYS_PCIE2_NAME
case PCIE2:
return CONFIG_SYS_PCIE2_NAME;
#endif
#ifdef CONFIG_SYS_PCIE3_NAME
case PCIE3:
return CONFIG_SYS_PCIE3_NAME;
#endif
#ifdef CONFIG_SYS_PCIE4_NAME
case PCIE4:
return CONFIG_SYS_PCIE4_NAME;
#endif
default:
return NULL;
}
return NULL;
}
__attribute__((weak, alias("__board_serdes_name"))) const char *
board_serdes_name(enum srds_prtcl device);
static u32 devdisr_mask[] = {
_DEVDISR_PCIE1,
_DEVDISR_PCIE2,
_DEVDISR_PCIE3,
_DEVDISR_PCIE4,
};
int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
struct fsl_pci_info *pci_info)
{
struct pci_controller *hose;
int num = dev - PCIE1;
hose = calloc(1, sizeof(struct pci_controller));
if (!hose)
return busno;
if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
busno = fsl_configure_pcie(pci_info, hose,
board_serdes_name(dev), busno);
} else {
fsl_pci: Update PCIe boot ouput This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-28 23:47:25 +00:00
printf("PCIe%d: disabled\n", num + 1);
powerpc/fsl-pci: Add generic code to setup PCIe controllers Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-15 20:21:41 +00:00
}
return busno;
}
int fsl_pcie_init_board(int busno)
{
struct fsl_pci_info pci_info;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:19 +00:00
u32 devdisr;
u32 *addr;
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
addr = &gur->devdisr3;
#else
addr = &gur->devdisr;
#endif
devdisr = in_be32(addr);
powerpc/fsl-pci: Add generic code to setup PCIe controllers Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-15 20:21:41 +00:00
#ifdef CONFIG_PCIE1
SET_STD_PCIE_INFO(pci_info, 1);
busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
#else
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:19 +00:00
setbits_be32(addr, _DEVDISR_PCIE1); /* disable */
powerpc/fsl-pci: Add generic code to setup PCIe controllers Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-15 20:21:41 +00:00
#endif
#ifdef CONFIG_PCIE2
SET_STD_PCIE_INFO(pci_info, 2);
busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
#else
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:19 +00:00
setbits_be32(addr, _DEVDISR_PCIE2); /* disable */
powerpc/fsl-pci: Add generic code to setup PCIe controllers Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-15 20:21:41 +00:00
#endif
#ifdef CONFIG_PCIE3
SET_STD_PCIE_INFO(pci_info, 3);
busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
#else
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:19 +00:00
setbits_be32(addr, _DEVDISR_PCIE3); /* disable */
powerpc/fsl-pci: Add generic code to setup PCIe controllers Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-15 20:21:41 +00:00
#endif
#ifdef CONFIG_PCIE4
SET_STD_PCIE_INFO(pci_info, 4);
busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
#else
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:19 +00:00
setbits_be32(addr, _DEVDISR_PCIE4); /* disable */
powerpc/fsl-pci: Add generic code to setup PCIe controllers Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-12-15 20:21:41 +00:00
#endif
return busno;
}
#else
int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
struct fsl_pci_info *pci_info)
{
return busno;
}
int fsl_pcie_init_board(int busno)
{
return busno;
}
#endif
pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-ranges Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-23 05:01:06 +00:00
#ifdef CONFIG_OF_BOARD_SETUP
libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h> Thomas reported U-Boot failed to build host tools if libfdt-devel package is installed because tools include libfdt headers from /usr/include/ instead of using internal ones. This commit moves the header code: include/libfdt.h -> include/linux/libfdt.h include/libfdt_env.h -> include/linux/libfdt_env.h and replaces include directives: #include <libfdt.h> -> #include <linux/libfdt.h> #include <libfdt_env.h> -> #include <linux/libfdt_env.h> Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-04 16:20:11 +00:00
#include <linux/libfdt.h>
pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-ranges Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-23 05:01:06 +00:00
#include <fdt_support.h>
powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliases Previously we used an alias the pci node to determine which node to fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to find the node to update. Additionally, we replace the code in each board with a single macro call that makes assumes uniform naming and reduces duplication in this area. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-09 03:37:44 +00:00
void ft_fsl_pci_setup(void *blob, const char *pci_compat,
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
2010-12-17 11:57:25 +00:00
unsigned long ctrl_addr)
pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-ranges Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-23 05:01:06 +00:00
{
powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliases Previously we used an alias the pci node to determine which node to fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to find the node to update. Additionally, we replace the code in each board with a single macro call that makes assumes uniform naming and reduces duplication in this area. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-09 03:37:44 +00:00
int off;
ppc/8xxx: Delete PCI nodes from device tree if not configured If the PCI controller wasn't configured or enabled delete from the device tree (include its alias). For the case that we didn't even configure u-boot with knowledge of the controller we can use the fact that the pci_controller pointer is NULL to delete the node in the device tree. We determine that a controller was not setup (because of HW config) based on the fact that cfg_addr wasn't setup. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-03-30 15:07:12 +00:00
u32 bus_range[2];
powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliases Previously we used an alias the pci node to determine which node to fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to find the node to update. Additionally, we replace the code in each board with a single macro call that makes assumes uniform naming and reduces duplication in this area. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-09 03:37:44 +00:00
phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
2010-12-17 11:57:25 +00:00
struct pci_controller *hose;
hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliases Previously we used an alias the pci node to determine which node to fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to find the node to update. Additionally, we replace the code in each board with a single macro call that makes assumes uniform naming and reduces duplication in this area. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-09 03:37:44 +00:00
/* convert ctrl_addr to true physical address */
p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-ranges Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-23 05:01:06 +00:00
ppc/8xxx: Delete PCI nodes from device tree if not configured If the PCI controller wasn't configured or enabled delete from the device tree (include its alias). For the case that we didn't even configure u-boot with knowledge of the controller we can use the fact that the pci_controller pointer is NULL to delete the node in the device tree. We determine that a controller was not setup (because of HW config) based on the fact that cfg_addr wasn't setup. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-03-30 15:07:12 +00:00
if (off < 0)
return;
pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-ranges Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-23 05:01:06 +00:00
ppc/8xxx: Delete PCI nodes from device tree if not configured If the PCI controller wasn't configured or enabled delete from the device tree (include its alias). For the case that we didn't even configure u-boot with knowledge of the controller we can use the fact that the pci_controller pointer is NULL to delete the node in the device tree. We determine that a controller was not setup (because of HW config) based on the fact that cfg_addr wasn't setup. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-03-30 15:07:12 +00:00
/* We assume a cfg_addr not being set means we didn't setup the controller */
if ((hose == NULL) || (hose->cfg_addr == NULL)) {
powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliases Previously we used an alias the pci node to determine which node to fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to find the node to update. Additionally, we replace the code in each board with a single macro call that makes assumes uniform naming and reduces duplication in this area. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-09 03:37:44 +00:00
fdt_del_node(blob, off);
ppc/8xxx: Delete PCI nodes from device tree if not configured If the PCI controller wasn't configured or enabled delete from the device tree (include its alias). For the case that we didn't even configure u-boot with knowledge of the controller we can use the fact that the pci_controller pointer is NULL to delete the node in the device tree. We determine that a controller was not setup (because of HW config) based on the fact that cfg_addr wasn't setup. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-03-30 15:07:12 +00:00
} else {
pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-ranges Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-23 05:01:06 +00:00
bus_range[0] = 0;
bus_range[1] = hose->last_busno - hose->first_busno;
fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
fdt_pci_dma_ranges(blob, off, hose);
}
}
#endif
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