2020-08-05 17:14:28 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J7200 SoC Family Main Domain peripherals
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*
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* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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2021-07-21 15:58:41 +00:00
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/ {
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serdes_refclk: serdes-refclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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};
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2020-08-05 17:14:28 +00:00
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&cbass_main {
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msmc_ram: sram@70000000 {
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compatible = "mmio-sram";
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2021-02-01 05:56:41 +00:00
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reg = <0x00 0x70000000 0x00 0x100000>;
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2020-08-05 17:14:28 +00:00
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#address-cells = <1>;
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#size-cells = <1>;
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2021-02-01 05:56:41 +00:00
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ranges = <0x00 0x00 0x70000000 0x100000>;
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2020-08-05 17:14:28 +00:00
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atf-sram@0 {
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2021-02-01 05:56:41 +00:00
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reg = <0x00 0x20000>;
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};
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};
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scm_conf: scm-conf@100000 {
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compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
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reg = <0x00 0x00100000 0x00 0x1c000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x00100000 0x1c000>;
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serdes_ln_ctrl: serdes-ln-ctrl@4080 {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
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<0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
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};
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usb_serdes_mux: mux-controller@4000 {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
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2020-08-05 17:14:28 +00:00
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};
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};
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01900000 0x00 0x100000>; /* GICR */
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/* vcpumntirq: virtual CPU interface maintenance interrupt */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: msi-controller@1820000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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2021-02-01 05:56:41 +00:00
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main_gpio_intr: interrupt-controller0 {
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compatible = "ti,sci-intr";
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <131>;
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ti,interrupt-ranges = <8 392 56>;
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};
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main_navss: bus@30000000 {
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2020-08-05 17:14:28 +00:00
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
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2021-02-01 05:56:41 +00:00
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ti,sci-dev-id = <199>;
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main_navss_intr: interrupt-controller1 {
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compatible = "ti,sci-intr";
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ti,intr-trigger-type = <4>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <213>;
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ti,interrupt-ranges = <0 64 64>,
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<64 448 64>,
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<128 672 64>;
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};
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main_udmass_inta: msi-controller@33d00000 {
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compatible = "ti,sci-inta";
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reg = <0x00 0x33d00000 0x00 0x100000>;
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interrupt-controller;
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#interrupt-cells = <0>;
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interrupt-parent = <&main_navss_intr>;
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msi-controller;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <209>;
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ti,interrupt-ranges = <0 0 256>;
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};
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2020-08-05 17:14:28 +00:00
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secure_proxy_main: mailbox@32c00000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x32c00000 0x00 0x100000>,
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<0x00 0x32400000 0x00 0x100000>,
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<0x00 0x32800000 0x00 0x100000>;
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interrupt-names = "rx_011";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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};
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2021-02-01 05:56:41 +00:00
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hwspinlock: spinlock@30e00000 {
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compatible = "ti,am654-hwspinlock";
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reg = <0x00 0x30e00000 0x00 0x1000>;
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#hwlock-cells = <1>;
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};
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mailbox0_cluster0: mailbox@31f80000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f80000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster1: mailbox@31f81000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f81000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster2: mailbox@31f82000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f82000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster3: mailbox@31f83000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f83000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster4: mailbox@31f84000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f84000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster5: mailbox@31f85000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f85000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster6: mailbox@31f86000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f86000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster7: mailbox@31f87000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f87000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster8: mailbox@31f88000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f88000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster9: mailbox@31f89000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f89000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster10: mailbox@31f8a000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f8a000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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mailbox0_cluster11: mailbox@31f8b000 {
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compatible = "ti,am654-mailbox";
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reg = <0x00 0x31f8b000 0x00 0x200>;
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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interrupt-parent = <&main_navss_intr>;
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};
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main_ringacc: ringacc@3c000000 {
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compatible = "ti,am654-navss-ringacc";
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reg = <0x00 0x3c000000 0x00 0x400000>,
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<0x00 0x38000000 0x00 0x400000>,
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<0x00 0x31120000 0x00 0x100>,
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<0x00 0x33000000 0x00 0x40000>;
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reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
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ti,num-rings = <1024>;
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ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <211>;
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msi-parent = <&main_udmass_inta>;
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};
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main_udmap: dma-controller@31150000 {
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compatible = "ti,j721e-navss-main-udmap";
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reg = <0x00 0x31150000 0x00 0x100>,
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<0x00 0x34000000 0x00 0x100000>,
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<0x00 0x35000000 0x00 0x100000>;
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reg-names = "gcfg", "rchanrt", "tchanrt";
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msi-parent = <&main_udmass_inta>;
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#dma-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <212>;
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ti,ringacc = <&main_ringacc>;
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ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
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<0x0f>, /* TX_HCHAN */
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<0x10>; /* TX_UHCHAN */
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ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
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<0x0b>, /* RX_HCHAN */
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<0x0c>; /* RX_UHCHAN */
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ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
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};
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cpts@310d0000 {
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compatible = "ti,j721e-cpts";
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reg = <0x00 0x310d0000 0x00 0x400>;
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reg-names = "cpts";
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clocks = <&k3_clks 201 1>;
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clock-names = "cpts";
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interrupts-extended = <&main_navss_intr 391>;
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interrupt-names = "cpts";
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ti,cpts-periodic-outputs = <6>;
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ti,cpts-ext-ts-inputs = <8>;
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};
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2020-08-05 17:14:28 +00:00
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};
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2021-02-01 05:56:41 +00:00
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main_pmx0: pinctrl@11c000 {
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2020-08-05 17:14:28 +00:00
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compatible = "pinctrl-single";
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/* Proxy 0 addressing */
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2021-02-01 05:56:41 +00:00
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reg = <0x00 0x11c000 0x00 0x2b4>;
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2020-08-05 17:14:28 +00:00
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_uart0: serial@2800000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02800000 0x00 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 146 2>;
|
|
|
|
|
clock-names = "fclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart1: serial@2810000 {
|
|
|
|
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02810000 0x00 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 278 2>;
|
|
|
|
|
clock-names = "fclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart2: serial@2820000 {
|
|
|
|
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02820000 0x00 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 279 2>;
|
|
|
|
|
clock-names = "fclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart3: serial@2830000 {
|
|
|
|
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02830000 0x00 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 280 2>;
|
|
|
|
|
clock-names = "fclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart4: serial@2840000 {
|
|
|
|
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02840000 0x00 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 281 2>;
|
|
|
|
|
clock-names = "fclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart5: serial@2850000 {
|
|
|
|
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02850000 0x00 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 282 2>;
|
|
|
|
|
clock-names = "fclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart6: serial@2860000 {
|
|
|
|
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02860000 0x00 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 283 2>;
|
|
|
|
|
clock-names = "fclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart7: serial@2870000 {
|
|
|
|
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02870000 0x00 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 284 2>;
|
|
|
|
|
clock-names = "fclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart8: serial@2880000 {
|
|
|
|
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02880000 0x00 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 285 2>;
|
|
|
|
|
clock-names = "fclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_uart9: serial@2890000 {
|
|
|
|
|
compatible = "ti,j721e-uart", "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02890000 0x00 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
|
|
|
|
power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 286 2>;
|
|
|
|
|
clock-names = "fclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_sdhci0: sdhci@4f80000 {
|
|
|
|
|
compatible = "ti,j721e-sdhci-8bit";
|
|
|
|
|
reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
|
|
|
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clock-names = "clk_xin", "clk_ahb";
|
|
|
|
|
clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
|
|
|
|
|
ti,otap-del-sel-legacy = <0x0>;
|
|
|
|
|
ti,otap-del-sel-mmc-hs = <0x0>;
|
|
|
|
|
ti,otap-del-sel-ddr52 = <0x6>;
|
|
|
|
|
ti,otap-del-sel-hs200 = <0x8>;
|
2021-05-25 09:38:24 +00:00
|
|
|
ti,otap-del-sel-hs400 = <0x5>;
|
|
|
|
|
ti,itap-del-sel-legacy = <0x10>;
|
|
|
|
|
ti,itap-del-sel-mmc-hs = <0xa>;
|
2020-08-05 17:14:28 +00:00
|
|
|
ti,strobe-sel = <0x77>;
|
2021-05-25 09:38:24 +00:00
|
|
|
ti,clkbuf-sel = <0x7>;
|
2020-08-05 17:14:28 +00:00
|
|
|
ti,trm-icp = <0x8>;
|
|
|
|
|
bus-width = <8>;
|
2021-05-25 09:38:24 +00:00
|
|
|
mmc-hs400-1_8v;
|
2020-08-05 17:14:28 +00:00
|
|
|
mmc-hs200-1_8v;
|
|
|
|
|
mmc-ddr-1_8v;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_sdhci1: sdhci@4fb0000 {
|
|
|
|
|
compatible = "ti,j721e-sdhci-4bit";
|
|
|
|
|
reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>;
|
|
|
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clock-names = "clk_xin", "clk_ahb";
|
|
|
|
|
clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
|
|
|
|
|
ti,otap-del-sel-legacy = <0x0>;
|
|
|
|
|
ti,otap-del-sel-sd-hs = <0x0>;
|
|
|
|
|
ti,otap-del-sel-sdr12 = <0xf>;
|
|
|
|
|
ti,otap-del-sel-sdr25 = <0xf>;
|
|
|
|
|
ti,otap-del-sel-sdr50 = <0xc>;
|
|
|
|
|
ti,otap-del-sel-sdr104 = <0x5>;
|
|
|
|
|
ti,otap-del-sel-ddr50 = <0xc>;
|
2021-05-25 09:38:24 +00:00
|
|
|
ti,itap-del-sel-legacy = <0x0>;
|
|
|
|
|
ti,itap-del-sel-sd-hs = <0x0>;
|
|
|
|
|
ti,itap-del-sel-sdr12 = <0x0>;
|
|
|
|
|
ti,itap-del-sel-sdr25 = <0x0>;
|
2021-02-04 09:41:00 +00:00
|
|
|
ti,clkbuf-sel = <0x7>;
|
2021-05-25 09:38:24 +00:00
|
|
|
ti,trm-icp = <0x8>;
|
2020-08-05 17:14:28 +00:00
|
|
|
dma-coherent;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_i2c0: i2c@2000000 {
|
|
|
|
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
2021-02-01 05:56:41 +00:00
|
|
|
reg = <0x00 0x2000000 0x00 0x100>;
|
2020-08-05 17:14:28 +00:00
|
|
|
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
clocks = <&k3_clks 187 1>;
|
2021-02-01 05:56:41 +00:00
|
|
|
power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
|
2020-08-05 17:14:28 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_i2c1: i2c@2010000 {
|
|
|
|
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
2021-02-01 05:56:41 +00:00
|
|
|
reg = <0x00 0x2010000 0x00 0x100>;
|
2020-08-05 17:14:28 +00:00
|
|
|
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
clocks = <&k3_clks 188 1>;
|
|
|
|
|
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_i2c2: i2c@2020000 {
|
|
|
|
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
2021-02-01 05:56:41 +00:00
|
|
|
reg = <0x00 0x2020000 0x00 0x100>;
|
2020-08-05 17:14:28 +00:00
|
|
|
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
clocks = <&k3_clks 189 1>;
|
|
|
|
|
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_i2c3: i2c@2030000 {
|
|
|
|
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
2021-02-01 05:56:41 +00:00
|
|
|
reg = <0x00 0x2030000 0x00 0x100>;
|
2020-08-05 17:14:28 +00:00
|
|
|
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
clocks = <&k3_clks 190 1>;
|
|
|
|
|
power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_i2c4: i2c@2040000 {
|
|
|
|
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
2021-02-01 05:56:41 +00:00
|
|
|
reg = <0x00 0x2040000 0x00 0x100>;
|
2020-08-05 17:14:28 +00:00
|
|
|
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
clocks = <&k3_clks 191 1>;
|
|
|
|
|
power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_i2c5: i2c@2050000 {
|
|
|
|
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
2021-02-01 05:56:41 +00:00
|
|
|
reg = <0x00 0x2050000 0x00 0x100>;
|
2020-08-05 17:14:28 +00:00
|
|
|
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
clocks = <&k3_clks 192 1>;
|
|
|
|
|
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_i2c6: i2c@2060000 {
|
|
|
|
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
2021-02-01 05:56:41 +00:00
|
|
|
reg = <0x00 0x2060000 0x00 0x100>;
|
2020-08-05 17:14:28 +00:00
|
|
|
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
clocks = <&k3_clks 193 1>;
|
|
|
|
|
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
};
|
2020-08-06 18:56:56 +00:00
|
|
|
|
2021-02-01 05:56:41 +00:00
|
|
|
main_gpio0: gpio@600000 {
|
|
|
|
|
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
|
|
|
|
|
reg = <0x0 0x00600000 0x0 0x100>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
|
|
|
|
|
<105 1 IRQ_TYPE_EDGE_RISING>,
|
|
|
|
|
<105 2 IRQ_TYPE_EDGE_RISING>,
|
|
|
|
|
<105 3 IRQ_TYPE_EDGE_RISING>,
|
|
|
|
|
<105 4 IRQ_TYPE_EDGE_RISING>,
|
|
|
|
|
<105 5 IRQ_TYPE_EDGE_RISING>,
|
|
|
|
|
<105 6 IRQ_TYPE_EDGE_RISING>,
|
|
|
|
|
<105 7 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ti,ngpio = <69>;
|
|
|
|
|
ti,davinci-gpio-unbanked = <0>;
|
|
|
|
|
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 105 0>;
|
|
|
|
|
clock-names = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
2021-07-21 15:58:41 +00:00
|
|
|
serdes_wiz0: wiz@5060000 {
|
|
|
|
|
compatible = "ti,j721e-wiz-10g";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
|
|
|
|
|
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
|
|
|
|
num-lanes = <4>;
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
ranges = <0x5060000 0x0 0x5060000 0x10000>;
|
|
|
|
|
|
|
|
|
|
assigned-clocks = <&k3_clks 292 85>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 292 89>;
|
|
|
|
|
|
|
|
|
|
wiz0_pll0_refclk: pll0-refclk {
|
|
|
|
|
clocks = <&k3_clks 292 85>, <&serdes_refclk>;
|
|
|
|
|
clock-output-names = "wiz0_pll0_refclk";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
assigned-clocks = <&wiz0_pll0_refclk>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 292 85>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
wiz0_pll1_refclk: pll1-refclk {
|
|
|
|
|
clocks = <&k3_clks 292 85>, <&serdes_refclk>;
|
|
|
|
|
clock-output-names = "wiz0_pll1_refclk";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
assigned-clocks = <&wiz0_pll1_refclk>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 292 85>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
wiz0_refclk_dig: refclk-dig {
|
|
|
|
|
clocks = <&k3_clks 292 85>, <&serdes_refclk>;
|
|
|
|
|
clock-output-names = "wiz0_refclk_dig";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
assigned-clocks = <&wiz0_refclk_dig>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 292 85>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
|
|
|
|
|
clocks = <&wiz0_refclk_dig>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
serdes0: serdes@5060000 {
|
|
|
|
|
compatible = "ti,j721e-serdes-10g";
|
|
|
|
|
reg = <0x05060000 0x00010000>;
|
|
|
|
|
reg-names = "torrent_phy";
|
|
|
|
|
resets = <&serdes_wiz0 0>;
|
|
|
|
|
reset-names = "torrent_reset";
|
|
|
|
|
clocks = <&wiz0_pll0_refclk>;
|
|
|
|
|
clock-names = "refclk";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2021-02-01 05:56:41 +00:00
|
|
|
usbss0: cdns-usb@4104000 {
|
2020-08-06 18:56:56 +00:00
|
|
|
compatible = "ti,j721e-usb";
|
|
|
|
|
reg = <0x00 0x4104000 0x00 0x100>;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
|
2021-02-01 05:56:41 +00:00
|
|
|
clock-names = "ref", "lpm";
|
2020-08-06 18:56:56 +00:00
|
|
|
assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
|
|
|
|
|
assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
|
|
usb0: usb@6000000 {
|
|
|
|
|
compatible = "cdns,usb3";
|
|
|
|
|
reg = <0x00 0x6000000 0x00 0x10000>,
|
|
|
|
|
<0x00 0x6010000 0x00 0x10000>,
|
|
|
|
|
<0x00 0x6020000 0x00 0x10000>;
|
|
|
|
|
reg-names = "otg", "xhci", "dev";
|
|
|
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
|
|
|
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
|
|
|
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
|
|
|
|
|
interrupt-names = "host",
|
|
|
|
|
"peripheral",
|
|
|
|
|
"otg";
|
|
|
|
|
maximum-speed = "super-speed";
|
|
|
|
|
dr_mode = "otg";
|
|
|
|
|
};
|
|
|
|
|
};
|
2020-08-17 23:15:11 +00:00
|
|
|
|
|
|
|
|
main_r5fss0: r5fss@5c00000 {
|
|
|
|
|
compatible = "ti,j7200-r5fss";
|
2021-01-27 00:20:56 +00:00
|
|
|
ti,cluster-mode = <0>;
|
2020-08-17 23:15:11 +00:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
|
|
|
|
|
<0x5d00000 0x00 0x5d00000 0x20000>;
|
|
|
|
|
power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
|
|
|
|
|
main_r5fss0_core0: r5f@5c00000 {
|
|
|
|
|
compatible = "ti,j7200-r5f";
|
|
|
|
|
reg = <0x5c00000 0x00010000>,
|
|
|
|
|
<0x5c10000 0x00010000>;
|
|
|
|
|
reg-names = "atcm", "btcm";
|
|
|
|
|
ti,sci = <&dmsc>;
|
|
|
|
|
ti,sci-dev-id = <245>;
|
|
|
|
|
ti,sci-proc-ids = <0x06 0xFF>;
|
|
|
|
|
resets = <&k3_reset 245 1>;
|
|
|
|
|
firmware-name = "j7200-main-r5f0_0-fw";
|
2021-01-27 00:20:56 +00:00
|
|
|
ti,atcm-enable = <1>;
|
|
|
|
|
ti,btcm-enable = <1>;
|
|
|
|
|
ti,loczrama = <1>;
|
2020-08-17 23:15:11 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_r5fss0_core1: r5f@5d00000 {
|
|
|
|
|
compatible = "ti,j7200-r5f";
|
|
|
|
|
reg = <0x5d00000 0x00008000>,
|
|
|
|
|
<0x5d10000 0x00008000>;
|
|
|
|
|
reg-names = "atcm", "btcm";
|
|
|
|
|
ti,sci = <&dmsc>;
|
|
|
|
|
ti,sci-dev-id = <246>;
|
|
|
|
|
ti,sci-proc-ids = <0x07 0xFF>;
|
|
|
|
|
resets = <&k3_reset 246 1>;
|
|
|
|
|
firmware-name = "j7200-main-r5f0_1-fw";
|
2021-01-27 00:20:56 +00:00
|
|
|
ti,atcm-enable = <1>;
|
|
|
|
|
ti,btcm-enable = <1>;
|
|
|
|
|
ti,loczrama = <1>;
|
2020-08-17 23:15:11 +00:00
|
|
|
};
|
|
|
|
|
};
|
2020-08-05 17:14:28 +00:00
|
|
|
};
|
