2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2017-05-09 11:36:21 +00:00
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/*
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* U-Boot Marvell 37xx SoC pinctrl driver
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*
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* Copyright (C) 2017 Stefan Roese <sr@denx.de>
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*
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* This driver is based on the Linux driver version, which is:
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* Copyright (C) 2017 Marvell
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* Additionally parts are derived from the Meson U-Boot pinctrl driver,
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* which is:
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* (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
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* Based on code from Linux kernel:
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* Copyright (C) 2016 Endless Mobile, Inc.
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* https://spdx.org/licenses
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*/
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#include <common.h>
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#include <config.h>
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#include <dm.h>
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2020-02-03 14:36:16 +00:00
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#include <malloc.h>
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2020-10-31 03:38:53 +00:00
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#include <asm/global_data.h>
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2017-05-17 15:05:25 +00:00
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#include <dm/device-internal.h>
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2020-02-03 14:36:16 +00:00
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#include <dm/device_compat.h>
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2020-02-03 14:36:15 +00:00
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#include <dm/devres.h>
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2017-05-17 15:05:25 +00:00
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#include <dm/lists.h>
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2017-05-09 11:36:21 +00:00
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#include <dm/pinctrl.h>
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#include <dm/root.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <regmap.h>
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2017-05-17 15:05:25 +00:00
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#include <asm/gpio.h>
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2017-05-09 11:36:21 +00:00
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#include <asm/system.h>
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#include <asm/io.h>
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2020-05-10 17:40:13 +00:00
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#include <linux/bitops.h>
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2020-05-10 17:40:01 +00:00
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#include <linux/libfdt.h>
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2017-05-09 11:36:21 +00:00
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DECLARE_GLOBAL_DATA_PTR;
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#define OUTPUT_EN 0x0
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2017-05-17 15:05:25 +00:00
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#define INPUT_VAL 0x10
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#define OUTPUT_VAL 0x18
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2017-05-09 11:36:21 +00:00
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#define OUTPUT_CTL 0x20
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#define SELECTION 0x30
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#define IRQ_EN 0x0
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#define IRQ_POL 0x08
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#define IRQ_STATUS 0x10
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#define IRQ_WKUP 0x18
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2018-03-26 07:56:01 +00:00
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#define NB_FUNCS 3
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2017-05-09 11:36:21 +00:00
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#define GPIO_PER_REG 32
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/**
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* struct armada_37xx_pin_group: represents group of pins of a pinmux function.
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* The pins of a pinmux groups are composed of one or two groups of contiguous
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* pins.
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* @name: Name of the pin group, used to lookup the group.
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* @start_pins: Index of the first pin of the main range of pins belonging to
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* the group
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* @npins: Number of pins included in the first range
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* @reg_mask: Bit mask matching the group in the selection register
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* @extra_pins: Index of the first pin of the optional second range of pins
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* belonging to the group
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* @npins: Number of pins included in the second optional range
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* @funcs: A list of pinmux functions that can be selected for this group.
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*/
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struct armada_37xx_pin_group {
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const char *name;
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unsigned int start_pin;
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unsigned int npins;
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u32 reg_mask;
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u32 val[NB_FUNCS];
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unsigned int extra_pin;
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unsigned int extra_npins;
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const char *funcs[NB_FUNCS];
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};
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struct armada_37xx_pin_data {
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u8 nr_pins;
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char *name;
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struct armada_37xx_pin_group *groups;
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int ngroups;
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};
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struct armada_37xx_pmx_func {
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const char *name;
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const char **groups;
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unsigned int ngroups;
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};
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struct armada_37xx_pinctrl {
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void __iomem *base;
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const struct armada_37xx_pin_data *data;
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struct udevice *dev;
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struct pinctrl_dev *pctl_dev;
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struct armada_37xx_pmx_func *funcs;
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unsigned int nfuncs;
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};
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2022-07-25 12:09:01 +00:00
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#define PIN_GRP_GPIO_0(_name, _start, _nr) \
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{ \
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.name = _name, \
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.start_pin = _start, \
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.npins = _nr, \
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.reg_mask = 0, \
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.val = {0}, \
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.funcs = {"gpio"} \
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}
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2017-05-09 11:36:21 +00:00
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#define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
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{ \
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.name = _name, \
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.start_pin = _start, \
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.npins = _nr, \
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.reg_mask = _mask, \
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.val = {0, _mask}, \
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.funcs = {_func1, "gpio"} \
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}
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#define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
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{ \
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.name = _name, \
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.start_pin = _start, \
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.npins = _nr, \
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.reg_mask = _mask, \
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.val = {_val1, _val2}, \
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.funcs = {_func1, "gpio"} \
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}
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2018-03-26 07:56:01 +00:00
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#define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
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{ \
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.name = _name, \
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.start_pin = _start, \
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.npins = _nr, \
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.reg_mask = _mask, \
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.val = {_v1, _v2, _v3}, \
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.funcs = {_f1, _f2, "gpio"} \
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}
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2017-05-09 11:36:21 +00:00
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#define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
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_f1, _f2) \
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{ \
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.name = _name, \
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.start_pin = _start, \
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.npins = _nr, \
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.reg_mask = _mask, \
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.val = {_v1, _v2}, \
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.extra_pin = _start2, \
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.extra_npins = _nr2, \
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.funcs = {_f1, _f2} \
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}
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static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
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PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
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PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
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PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
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2021-07-23 17:57:11 +00:00
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PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
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"pwm", "led"),
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2022-02-28 14:59:37 +00:00
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PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
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2021-07-23 17:57:11 +00:00
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"pwm", "led"),
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2022-02-28 14:59:37 +00:00
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PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
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2021-07-23 17:57:11 +00:00
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"pwm", "led"),
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2022-02-28 14:59:37 +00:00
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PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
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2021-07-23 17:57:11 +00:00
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"pwm", "led"),
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2018-03-26 07:56:03 +00:00
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PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
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PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
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2022-07-25 12:09:01 +00:00
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PIN_GRP_GPIO_0("gpio1_5", 5, 1),
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2017-05-09 11:36:21 +00:00
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PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
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PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
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PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
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PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
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PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
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PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
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PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
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PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
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2017-06-22 09:13:35 +00:00
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PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
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BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
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18, 2, "gpio", "uart"),
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2017-05-09 11:36:21 +00:00
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};
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static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
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PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
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PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
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2022-07-25 12:09:01 +00:00
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PIN_GRP_GPIO_0("gpio2_2", 2, 1),
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2018-03-26 07:56:03 +00:00
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PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
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PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
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PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
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2022-07-25 12:09:01 +00:00
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PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
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PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
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PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
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2022-08-04 10:41:54 +00:00
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PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"),
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PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12),
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"ptp", "mii"),
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PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13),
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"ptp", "mii"),
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2018-03-26 07:56:01 +00:00
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PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
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"mii", "mii_err"),
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2017-05-09 11:36:21 +00:00
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};
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2022-07-25 12:09:00 +00:00
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static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
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2017-05-09 11:36:21 +00:00
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.nr_pins = 36,
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.name = "GPIO1",
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.groups = armada_37xx_nb_groups,
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.ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
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};
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2022-07-25 12:09:00 +00:00
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static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
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2018-03-26 07:55:59 +00:00
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.nr_pins = 30,
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2017-05-09 11:36:21 +00:00
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.name = "GPIO2",
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.groups = armada_37xx_sb_groups,
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.ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
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};
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2017-05-17 15:05:25 +00:00
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static inline void armada_37xx_update_reg(unsigned int *reg,
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2018-03-26 07:56:02 +00:00
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unsigned int *offset)
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2017-05-17 15:05:25 +00:00
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{
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/* We never have more than 2 registers */
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2018-03-26 07:56:02 +00:00
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if (*offset >= GPIO_PER_REG) {
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*offset -= GPIO_PER_REG;
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2017-05-17 15:05:25 +00:00
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*reg += sizeof(u32);
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}
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}
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2017-05-09 11:36:21 +00:00
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static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
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const char *func)
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{
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int f;
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2018-03-26 07:56:01 +00:00
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for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
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2017-05-09 11:36:21 +00:00
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if (!strcmp(grp->funcs[f], func))
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return f;
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return -ENOTSUPP;
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}
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static int armada_37xx_pmx_get_groups_count(struct udevice *dev)
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{
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struct armada_37xx_pinctrl *info = dev_get_priv(dev);
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2022-07-25 12:08:59 +00:00
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return info->data->ngroups;
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2017-05-09 11:36:21 +00:00
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}
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static const char *armada_37xx_pmx_dummy_name = "_dummy";
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static const char *armada_37xx_pmx_get_group_name(struct udevice *dev,
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unsigned selector)
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{
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struct armada_37xx_pinctrl *info = dev_get_priv(dev);
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2022-07-25 12:08:59 +00:00
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if (!info->data->groups[selector].name)
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2017-05-09 11:36:21 +00:00
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return armada_37xx_pmx_dummy_name;
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2022-07-25 12:08:59 +00:00
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return info->data->groups[selector].name;
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2017-05-09 11:36:21 +00:00
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}
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static int armada_37xx_pmx_get_funcs_count(struct udevice *dev)
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{
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struct armada_37xx_pinctrl *info = dev_get_priv(dev);
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return info->nfuncs;
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}
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static const char *armada_37xx_pmx_get_func_name(struct udevice *dev,
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unsigned selector)
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{
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struct armada_37xx_pinctrl *info = dev_get_priv(dev);
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return info->funcs[selector].name;
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}
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static int armada_37xx_pmx_set_by_name(struct udevice *dev,
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const char *name,
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2022-07-25 12:09:02 +00:00
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struct armada_37xx_pin_group *grp,
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bool warn_on_change)
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2017-05-09 11:36:21 +00:00
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{
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struct armada_37xx_pinctrl *info = dev_get_priv(dev);
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unsigned int reg = SELECTION;
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unsigned int mask = grp->reg_mask;
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2022-07-25 12:09:02 +00:00
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int func, val, old_func;
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2017-05-09 11:36:21 +00:00
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dev_dbg(info->dev, "enable function %s group %s\n",
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name, grp->name);
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func = armada_37xx_get_func_reg(grp, name);
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if (func < 0)
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return func;
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val = grp->val[func];
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2022-07-25 12:09:02 +00:00
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if (warn_on_change && val != (readl(info->base + reg) & mask)) {
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for (old_func = 0; (old_func < NB_FUNCS) && grp->funcs[old_func]; old_func++) {
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|
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if (grp->val[old_func] == val)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
dev_warn(info->dev, "Warning: Changing MPPs %u-%u function from %s to %s...\n",
|
|
|
|
grp->start_pin, grp->start_pin + grp->npins - 1,
|
|
|
|
((old_func < NB_FUNCS && grp->funcs[old_func]) ?
|
|
|
|
grp->funcs[old_func] : "unknown"),
|
|
|
|
name);
|
|
|
|
}
|
|
|
|
|
2017-05-09 11:36:21 +00:00
|
|
|
clrsetbits_le32(info->base + reg, mask, val);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int armada_37xx_pmx_group_set(struct udevice *dev,
|
|
|
|
unsigned group_selector,
|
|
|
|
unsigned func_selector)
|
|
|
|
{
|
|
|
|
struct armada_37xx_pinctrl *info = dev_get_priv(dev);
|
2022-07-25 12:08:59 +00:00
|
|
|
struct armada_37xx_pin_group *grp = &info->data->groups[group_selector];
|
2017-05-09 11:36:21 +00:00
|
|
|
const char *name = info->funcs[func_selector].name;
|
|
|
|
|
2022-07-25 12:09:02 +00:00
|
|
|
return armada_37xx_pmx_set_by_name(dev, name, grp, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int armada_37xx_pmx_gpio_request_enable(struct udevice *dev, unsigned int selector)
|
|
|
|
{
|
|
|
|
struct armada_37xx_pinctrl *info = dev_get_priv(dev);
|
|
|
|
int ret = -ENOTSUPP;
|
|
|
|
int n;
|
|
|
|
|
|
|
|
/* Find all groups where is requested selector pin and set each group to gpio function */
|
|
|
|
for (n = 0; n < info->data->ngroups; n++) {
|
|
|
|
struct armada_37xx_pin_group *grp = &info->data->groups[n];
|
|
|
|
|
|
|
|
if ((selector >= grp->start_pin && selector < grp->start_pin + grp->npins) ||
|
|
|
|
(selector >= grp->extra_pin && selector < grp->extra_pin + grp->extra_npins)) {
|
|
|
|
ret = armada_37xx_pmx_set_by_name(dev, "gpio", grp, true);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int armada_37xx_pmx_gpio_disable_free(struct udevice *dev, unsigned int selector)
|
|
|
|
{
|
|
|
|
/* nothing to do */
|
|
|
|
return 0;
|
2017-05-09 11:36:21 +00:00
|
|
|
}
|
|
|
|
|
2022-07-25 12:09:03 +00:00
|
|
|
static int armada_37xx_pmx_get_pins_count(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct armada_37xx_pinctrl *info = dev_get_priv(dev);
|
|
|
|
|
|
|
|
return info->data->nr_pins;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char *armada_37xx_pmx_get_pin_name(struct udevice *dev, unsigned int selector)
|
|
|
|
{
|
|
|
|
struct armada_37xx_pinctrl *info = dev_get_priv(dev);
|
|
|
|
static char buf[sizeof("MPPx_XX")];
|
|
|
|
|
|
|
|
sprintf(buf, "MPP%c_%u", info->data->name[4], selector);
|
|
|
|
return buf;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int armada_37xx_pmx_get_pin_muxing(struct udevice *dev, unsigned int selector,
|
|
|
|
char *buf, int size)
|
|
|
|
{
|
|
|
|
struct armada_37xx_pinctrl *info = dev_get_priv(dev);
|
|
|
|
int n;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* First check if selected pin is in some extra pin group.
|
|
|
|
* Function in extra pin group is active only when it is not gpio.
|
|
|
|
*/
|
|
|
|
for (n = 0; n < info->data->ngroups; n++) {
|
|
|
|
struct armada_37xx_pin_group *grp = &info->data->groups[n];
|
|
|
|
|
|
|
|
if (selector >= grp->extra_pin && selector < grp->extra_pin + grp->extra_npins) {
|
|
|
|
unsigned int reg = SELECTION;
|
|
|
|
unsigned int mask = grp->reg_mask;
|
|
|
|
int f, val;
|
|
|
|
|
|
|
|
val = (readl(info->base + reg) & mask);
|
|
|
|
|
|
|
|
for (f = 0; f < NB_FUNCS && grp->funcs[f]; f++) {
|
|
|
|
if (grp->val[f] == val) {
|
|
|
|
if (strcmp(grp->funcs[f], "gpio") != 0) {
|
|
|
|
strlcpy(buf, grp->funcs[f], size);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If pin is not active in some extra pin group then check regular groups. */
|
|
|
|
for (n = 0; n < info->data->ngroups; n++) {
|
|
|
|
struct armada_37xx_pin_group *grp = &info->data->groups[n];
|
|
|
|
|
|
|
|
if (selector >= grp->start_pin && selector < grp->start_pin + grp->npins) {
|
|
|
|
unsigned int reg = SELECTION;
|
|
|
|
unsigned int mask = grp->reg_mask;
|
|
|
|
int f, val;
|
|
|
|
|
|
|
|
val = (readl(info->base + reg) & mask);
|
|
|
|
|
|
|
|
for (f = 0; f < NB_FUNCS && grp->funcs[f]; f++) {
|
|
|
|
if (grp->val[f] == val) {
|
2022-08-04 10:41:56 +00:00
|
|
|
/*
|
|
|
|
* In more cases group name consist of
|
|
|
|
* function name followed by function
|
|
|
|
* number. So if function name is just
|
|
|
|
* prefix of group name, show group name.
|
|
|
|
*/
|
|
|
|
if (strncmp(grp->name, grp->funcs[f],
|
|
|
|
strlen(grp->funcs[f])) == 0)
|
|
|
|
strlcpy(buf, grp->name, size);
|
|
|
|
else
|
|
|
|
strlcpy(buf, grp->funcs[f], size);
|
2022-07-25 12:09:03 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
strlcpy(buf, "unknown", size);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
strlcpy(buf, "unknown", size);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-05-09 11:36:21 +00:00
|
|
|
/**
|
|
|
|
* armada_37xx_add_function() - Add a new function to the list
|
|
|
|
* @funcs: array of function to add the new one
|
|
|
|
* @funcsize: size of the remaining space for the function
|
|
|
|
* @name: name of the function to add
|
|
|
|
*
|
|
|
|
* If it is a new function then create it by adding its name else
|
|
|
|
* increment the number of group associated to this function.
|
|
|
|
*/
|
|
|
|
static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
|
|
|
|
int *funcsize, const char *name)
|
|
|
|
{
|
|
|
|
int i = 0;
|
|
|
|
|
|
|
|
if (*funcsize <= 0)
|
|
|
|
return -EOVERFLOW;
|
|
|
|
|
|
|
|
while (funcs->ngroups) {
|
|
|
|
/* function already there */
|
|
|
|
if (strcmp(funcs->name, name) == 0) {
|
|
|
|
funcs->ngroups++;
|
|
|
|
|
|
|
|
return -EEXIST;
|
|
|
|
}
|
|
|
|
funcs++;
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* append new unique function */
|
|
|
|
funcs->name = name;
|
|
|
|
funcs->ngroups = 1;
|
|
|
|
(*funcsize)--;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* armada_37xx_fill_group() - complete the group array
|
|
|
|
* @info: info driver instance
|
|
|
|
*
|
|
|
|
* Based on the data available from the armada_37xx_pin_group array
|
|
|
|
* completes the last member of the struct for each function: the list
|
|
|
|
* of the groups associated to this function.
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
|
|
|
|
{
|
|
|
|
int n, num = 0, funcsize = info->data->nr_pins;
|
|
|
|
|
2022-07-25 12:08:59 +00:00
|
|
|
for (n = 0; n < info->data->ngroups; n++) {
|
|
|
|
struct armada_37xx_pin_group *grp = &info->data->groups[n];
|
2022-07-25 12:08:58 +00:00
|
|
|
int f;
|
2017-05-09 11:36:21 +00:00
|
|
|
|
2018-03-26 07:56:01 +00:00
|
|
|
for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
|
2017-05-09 11:36:21 +00:00
|
|
|
int ret;
|
|
|
|
/* check for unique functions and count groups */
|
|
|
|
ret = armada_37xx_add_function(info->funcs, &funcsize,
|
|
|
|
grp->funcs[f]);
|
|
|
|
if (ret == -EOVERFLOW)
|
|
|
|
dev_err(info->dev,
|
|
|
|
"More functions than pins(%d)\n",
|
|
|
|
info->data->nr_pins);
|
|
|
|
if (ret < 0)
|
|
|
|
continue;
|
|
|
|
num++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
info->nfuncs = num;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* armada_37xx_fill_funcs() - complete the funcs array
|
|
|
|
* @info: info driver instance
|
|
|
|
*
|
|
|
|
* Based on the data available from the armada_37xx_pin_group array
|
|
|
|
* completes the last two member of the struct for each group:
|
|
|
|
* - the list of the pins included in the group
|
|
|
|
* - the list of pinmux functions that can be selected for this group
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
|
|
|
|
{
|
|
|
|
struct armada_37xx_pmx_func *funcs = info->funcs;
|
|
|
|
int n;
|
|
|
|
|
|
|
|
for (n = 0; n < info->nfuncs; n++) {
|
|
|
|
const char *name = funcs[n].name;
|
|
|
|
const char **groups;
|
|
|
|
int g;
|
|
|
|
|
|
|
|
funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
|
|
|
|
sizeof(*(funcs[n].groups)),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!funcs[n].groups)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
groups = funcs[n].groups;
|
|
|
|
|
2022-07-25 12:08:59 +00:00
|
|
|
for (g = 0; g < info->data->ngroups; g++) {
|
|
|
|
struct armada_37xx_pin_group *gp = &info->data->groups[g];
|
2017-05-09 11:36:21 +00:00
|
|
|
int f;
|
|
|
|
|
2018-03-26 07:56:01 +00:00
|
|
|
for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
|
2017-05-09 11:36:21 +00:00
|
|
|
if (strcmp(gp->funcs[f], name) == 0) {
|
|
|
|
*groups = gp->name;
|
|
|
|
groups++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-05-17 15:05:25 +00:00
|
|
|
static int armada_37xx_gpio_get(struct udevice *dev, unsigned int offset)
|
|
|
|
{
|
|
|
|
struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
|
|
|
|
unsigned int reg = INPUT_VAL;
|
|
|
|
unsigned int val, mask;
|
|
|
|
|
2018-03-26 07:56:02 +00:00
|
|
|
armada_37xx_update_reg(®, &offset);
|
2017-05-17 15:05:25 +00:00
|
|
|
mask = BIT(offset);
|
|
|
|
|
|
|
|
val = readl(info->base + reg);
|
|
|
|
|
|
|
|
return (val & mask) != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int armada_37xx_gpio_set(struct udevice *dev, unsigned int offset,
|
|
|
|
int value)
|
|
|
|
{
|
|
|
|
struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
|
|
|
|
unsigned int reg = OUTPUT_VAL;
|
|
|
|
unsigned int mask, val;
|
|
|
|
|
2018-03-26 07:56:02 +00:00
|
|
|
armada_37xx_update_reg(®, &offset);
|
2017-05-17 15:05:25 +00:00
|
|
|
mask = BIT(offset);
|
|
|
|
val = value ? mask : 0;
|
|
|
|
|
|
|
|
clrsetbits_le32(info->base + reg, mask, val);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int armada_37xx_gpio_get_direction(struct udevice *dev,
|
|
|
|
unsigned int offset)
|
|
|
|
{
|
|
|
|
struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
|
|
|
|
unsigned int reg = OUTPUT_EN;
|
|
|
|
unsigned int val, mask;
|
|
|
|
|
2018-03-26 07:56:02 +00:00
|
|
|
armada_37xx_update_reg(®, &offset);
|
2017-05-17 15:05:25 +00:00
|
|
|
mask = BIT(offset);
|
|
|
|
val = readl(info->base + reg);
|
|
|
|
|
|
|
|
if (val & mask)
|
|
|
|
return GPIOF_OUTPUT;
|
|
|
|
else
|
|
|
|
return GPIOF_INPUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int armada_37xx_gpio_direction_input(struct udevice *dev,
|
|
|
|
unsigned int offset)
|
|
|
|
{
|
|
|
|
struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
|
|
|
|
unsigned int reg = OUTPUT_EN;
|
|
|
|
unsigned int mask;
|
|
|
|
|
2018-03-26 07:56:02 +00:00
|
|
|
armada_37xx_update_reg(®, &offset);
|
2017-05-17 15:05:25 +00:00
|
|
|
mask = BIT(offset);
|
|
|
|
|
|
|
|
clrbits_le32(info->base + reg, mask);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int armada_37xx_gpio_direction_output(struct udevice *dev,
|
|
|
|
unsigned int offset, int value)
|
|
|
|
{
|
|
|
|
struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
|
|
|
|
unsigned int reg = OUTPUT_EN;
|
|
|
|
unsigned int mask;
|
|
|
|
|
2018-03-26 07:56:02 +00:00
|
|
|
armada_37xx_update_reg(®, &offset);
|
2017-05-17 15:05:25 +00:00
|
|
|
mask = BIT(offset);
|
|
|
|
|
|
|
|
setbits_le32(info->base + reg, mask);
|
|
|
|
|
|
|
|
/* And set the requested value */
|
|
|
|
return armada_37xx_gpio_set(dev, offset, value);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int armada_37xx_gpio_probe(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
|
|
|
|
struct gpio_dev_priv *uc_priv;
|
|
|
|
|
|
|
|
uc_priv = dev_get_uclass_priv(dev);
|
|
|
|
uc_priv->bank_name = info->data->name;
|
|
|
|
uc_priv->gpio_count = info->data->nr_pins;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct dm_gpio_ops armada_37xx_gpio_ops = {
|
2022-07-25 12:09:02 +00:00
|
|
|
.request = pinctrl_gpio_request,
|
|
|
|
.rfree = pinctrl_gpio_free,
|
2017-05-17 15:05:25 +00:00
|
|
|
.set_value = armada_37xx_gpio_set,
|
|
|
|
.get_value = armada_37xx_gpio_get,
|
|
|
|
.get_function = armada_37xx_gpio_get_direction,
|
|
|
|
.direction_input = armada_37xx_gpio_direction_input,
|
|
|
|
.direction_output = armada_37xx_gpio_direction_output,
|
|
|
|
};
|
|
|
|
|
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static struct driver armada_37xx_gpio_driver = {
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.name = "armada-37xx-gpio",
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.id = UCLASS_GPIO,
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.probe = armada_37xx_gpio_probe,
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.ops = &armada_37xx_gpio_ops,
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};
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static int armada_37xx_gpiochip_register(struct udevice *parent,
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struct armada_37xx_pinctrl *info)
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{
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(parent);
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struct uclass_driver *drv;
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struct udevice *dev;
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int ret = -ENODEV;
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int subnode;
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char *name;
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2020-11-29 00:50:03 +00:00
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/* FIXME: Should not need to lookup GPIO uclass */
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2017-05-17 15:05:25 +00:00
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drv = lists_uclass_lookup(UCLASS_GPIO);
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if (!drv) {
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puts("Cannot find GPIO driver\n");
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return -ENOENT;
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}
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2020-11-29 00:50:03 +00:00
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/* FIXME: Use livtree and check the result of device_bind() below */
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2017-05-17 15:05:25 +00:00
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fdt_for_each_subnode(subnode, blob, node) {
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2017-06-22 09:13:36 +00:00
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if (fdtdec_get_bool(blob, subnode, "gpio-controller")) {
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2017-05-17 15:05:25 +00:00
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ret = 0;
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break;
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}
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};
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if (ret)
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return ret;
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name = calloc(1, 32);
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sprintf(name, "armada-37xx-gpio");
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/* Create child device UCLASS_GPIO and bind it */
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2020-11-29 00:50:03 +00:00
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device_bind(parent, &armada_37xx_gpio_driver, name, NULL,
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offset_to_ofnode(subnode), &dev);
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2017-05-17 15:05:25 +00:00
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return 0;
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}
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2022-07-25 12:09:00 +00:00
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static const struct pinctrl_ops armada_37xx_pinctrl_ops = {
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2022-07-25 12:09:03 +00:00
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.get_pins_count = armada_37xx_pmx_get_pins_count,
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.get_pin_name = armada_37xx_pmx_get_pin_name,
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.get_pin_muxing = armada_37xx_pmx_get_pin_muxing,
|
2017-05-09 11:36:21 +00:00
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.get_groups_count = armada_37xx_pmx_get_groups_count,
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.get_group_name = armada_37xx_pmx_get_group_name,
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.get_functions_count = armada_37xx_pmx_get_funcs_count,
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.get_function_name = armada_37xx_pmx_get_func_name,
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.pinmux_group_set = armada_37xx_pmx_group_set,
|
2022-07-25 12:09:02 +00:00
|
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.gpio_request_enable = armada_37xx_pmx_gpio_request_enable,
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.gpio_disable_free = armada_37xx_pmx_gpio_disable_free,
|
2017-05-09 11:36:21 +00:00
|
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|
.set_state = pinctrl_generic_set_state,
|
|
|
|
};
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|
2022-07-25 12:09:00 +00:00
|
|
|
static int armada_37xx_pinctrl_probe(struct udevice *dev)
|
2017-05-09 11:36:21 +00:00
|
|
|
{
|
|
|
|
struct armada_37xx_pinctrl *info = dev_get_priv(dev);
|
|
|
|
const struct armada_37xx_pin_data *pin_data;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
info->data = (struct armada_37xx_pin_data *)dev_get_driver_data(dev);
|
|
|
|
pin_data = info->data;
|
|
|
|
|
2020-07-17 05:36:46 +00:00
|
|
|
info->base = dev_read_addr_ptr(dev);
|
2017-05-09 11:36:21 +00:00
|
|
|
if (!info->base) {
|
2017-09-16 05:10:41 +00:00
|
|
|
pr_err("unable to find regmap\n");
|
2017-05-09 11:36:21 +00:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* we allocate functions for number of pins and hope there are
|
|
|
|
* fewer unique functions than pins available
|
|
|
|
*/
|
|
|
|
info->funcs = devm_kzalloc(info->dev, pin_data->nr_pins *
|
|
|
|
sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
|
|
|
|
if (!info->funcs)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
|
|
ret = armada_37xx_fill_group(info);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = armada_37xx_fill_func(info);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2017-05-17 15:05:25 +00:00
|
|
|
ret = armada_37xx_gpiochip_register(dev, info);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2017-05-09 11:36:21 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct udevice_id armada_37xx_pinctrl_of_match[] = {
|
|
|
|
{
|
|
|
|
.compatible = "marvell,armada3710-sb-pinctrl",
|
|
|
|
.data = (ulong)&armada_37xx_pin_sb,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "marvell,armada3710-nb-pinctrl",
|
|
|
|
.data = (ulong)&armada_37xx_pin_nb,
|
|
|
|
},
|
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(armada_37xx_pinctrl) = {
|
|
|
|
.name = "armada-37xx-pinctrl",
|
|
|
|
.id = UCLASS_PINCTRL,
|
|
|
|
.of_match = of_match_ptr(armada_37xx_pinctrl_of_match),
|
|
|
|
.probe = armada_37xx_pinctrl_probe,
|
2020-12-03 23:55:17 +00:00
|
|
|
.priv_auto = sizeof(struct armada_37xx_pinctrl),
|
2017-05-09 11:36:21 +00:00
|
|
|
.ops = &armada_37xx_pinctrl_ops,
|
|
|
|
};
|