u-boot/board/openpiton/riscv64/Kconfig

if TARGET_OPENPITON_RISCV64

config SYS_BOARD
	default "riscv64"

config SYS_VENDOR
	default "openpiton"

config SYS_CPU
	default "generic"

config SYS_CONFIG_NAME
	default "openpiton-riscv64"

config TEXT_BASE
	default 0x81000000 if SPL
	default 0x80000000 if !RISCV_SMODE
	default 0x81000000 if RISCV_SMODE

config SPL_TEXT_BASE
	default 0x82000000

config SPL_OPENSBI_LOAD_ADDR
	default 0x80000000

config BOARD_SPECIFIC_OPTIONS # dummy
	def_bool y
	select ARCH_EARLY_INIT_R
	select SUPPORT_SPL
	imply CPU_RISCV
	imply RISCV_TIMER
	imply SPL_RISCV_ACLINT
	imply CMD_CPU
	imply SPL_CPU_SUPPORT
	imply SPL_SMP
	imply SPL_MMC
	imply SMP
	imply SPL_RISCV_MMODE

endif
board: riscv: add openpiton-riscv64 SoC support This patch adds openpiton-riscv64 SOC support. In particular, this board supports a standard bootflow through zsbl->u-boot SPL-> opensbi->u-boot proper->Linux. There are separate defconfigs for building u-boot SPL and u-boot proper Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 2021-07-01 04:54:19 +00:00			`if TARGET_OPENPITON_RISCV64`

			`config SYS_BOARD`
			`default "riscv64"`

			`config SYS_VENDOR`
			`default "openpiton"`

			`config SYS_CPU`
			`default "generic"`

			`config SYS_CONFIG_NAME`
			`default "openpiton-riscv64"`

Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <sjg@chromium.org> 2022-10-21 00:22:39 +00:00			`config TEXT_BASE`
board: riscv: add openpiton-riscv64 SoC support This patch adds openpiton-riscv64 SOC support. In particular, this board supports a standard bootflow through zsbl->u-boot SPL-> opensbi->u-boot proper->Linux. There are separate defconfigs for building u-boot SPL and u-boot proper Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 2021-07-01 04:54:19 +00:00			`default 0x81000000 if SPL`
			`default 0x80000000 if !RISCV_SMODE`
			`default 0x81000000 if RISCV_SMODE`

			`config SPL_TEXT_BASE`
			`default 0x82000000`

			`config SPL_OPENSBI_LOAD_ADDR`
			`default 0x80000000`

			`config BOARD_SPECIFIC_OPTIONS # dummy`
			`def_bool y`
			`select ARCH_EARLY_INIT_R`
			`select SUPPORT_SPL`
			`imply CPU_RISCV`
			`imply RISCV_TIMER`
riscv: Rename SiFive CLINT to RISC-V ALINT As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com> 2023-06-21 15:11:46 +00:00			`imply SPL_RISCV_ACLINT`
board: riscv: add openpiton-riscv64 SoC support This patch adds openpiton-riscv64 SOC support. In particular, this board supports a standard bootflow through zsbl->u-boot SPL-> opensbi->u-boot proper->Linux. There are separate defconfigs for building u-boot SPL and u-boot proper Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 2021-07-01 04:54:19 +00:00			`imply CMD_CPU`
			`imply SPL_CPU_SUPPORT`
			`imply SPL_SMP`
			`imply SPL_MMC`
			`imply SMP`
			`imply SPL_RISCV_MMODE`

			`endif`