mirror of
https://github.com/AsahiLinux/m1n1
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a489a646bd
Signed-off-by: Hector Martin <marcan@marcan.st>
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254 KiB
JSON
1 line
No EOL
254 KiB
JSON
[{"index": 0, "name": "ACCDATA_EL1", "fullname": "Accelerator Data", "enc": [3, 0, 13, 0, 5], "fieldsets": [{"fields": [{"name": "ACCDATA", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ACTLR_EL1", "fullname": "Auxiliary Control Register (EL1)", "enc": [3, 0, 1, 0, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "ACTLR_EL2", "fullname": "Auxiliary Control Register (EL2)", "enc": [3, 4, 1, 0, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "ACTLR_EL3", "fullname": "Auxiliary Control Register (EL3)", "enc": [3, 6, 1, 0, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AFSR0_EL1", "fullname": "Auxiliary Fault Status Register 0 (EL1)", "enc": [3, 0, 5, 1, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AFSR0_EL12", "fullname": "Auxiliary Fault Status Register 0 (EL1)", "enc": [3, 5, 5, 1, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AFSR0_EL1", "fullname": "Auxiliary Fault Status Register 0 (EL2)", "enc": [3, 0, 5, 1, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AFSR0_EL2", "fullname": "Auxiliary Fault Status Register 0 (EL2)", "enc": [3, 4, 5, 1, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AFSR0_EL3", "fullname": "Auxiliary Fault Status Register 0 (EL3)", "enc": [3, 6, 5, 1, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AFSR1_EL1", "fullname": "Auxiliary Fault Status Register 1 (EL1)", "enc": [3, 0, 5, 1, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AFSR1_EL12", "fullname": "Auxiliary Fault Status Register 1 (EL1)", "enc": [3, 5, 5, 1, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AFSR1_EL1", "fullname": "Auxiliary Fault Status Register 1 (EL2)", "enc": [3, 0, 5, 1, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AFSR1_EL2", "fullname": "Auxiliary Fault Status Register 1 (EL2)", "enc": [3, 4, 5, 1, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AFSR1_EL3", "fullname": "Auxiliary Fault Status Register 1 (EL3)", "enc": [3, 6, 5, 1, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AIDR_EL1", "fullname": "Auxiliary ID Register", "enc": [3, 1, 0, 0, 7], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AMAIR_EL1", "fullname": "Auxiliary Memory Attribute Indirection Register (EL1)", "enc": [3, 0, 10, 3, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AMAIR_EL12", "fullname": "Auxiliary Memory Attribute Indirection Register (EL1)", "enc": [3, 5, 10, 3, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AMAIR_EL1", "fullname": "Auxiliary Memory Attribute Indirection Register (EL2)", "enc": [3, 0, 10, 3, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AMAIR_EL2", "fullname": "Auxiliary Memory Attribute Indirection Register (EL2)", "enc": [3, 4, 10, 3, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AMAIR_EL3", "fullname": "Auxiliary Memory Attribute Indirection Register (EL3)", "enc": [3, 6, 10, 3, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AMCFGR_EL0", "fullname": "Activity Monitors Configuration Register", "enc": [3, 3, 13, 2, 1], "fieldsets": [{"fields": [{"name": "NCG", "msb": 31, "lsb": 28}, {"name": "HDBG", "msb": 24, "lsb": 24}, {"name": "SIZE", "msb": 13, "lsb": 8}, {"name": "N", "msb": 7, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "AMCG1IDR_EL0", "fullname": "Activity Monitors Counter Group 1 Identification Register", "enc": [3, 3, 13, 2, 6], "fieldsets": [{"fields": [{"name": "AMEVCNTOFF1<n>_EL2", "msb": 31, "lsb": 16}, {"name": "AMEVCNTR1<n>_EL0", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "AMCGCR_EL0", "fullname": "Activity Monitors Counter Group Configuration Register", "enc": [3, 3, 13, 2, 2], "fieldsets": [{"fields": [{"name": "CG1NC", "msb": 15, "lsb": 8}, {"name": "CG0NC", "msb": 7, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "AMCNTENCLR0_EL0", "fullname": "Activity Monitors Count Enable Clear Register 0", "enc": [3, 3, 13, 2, 4], "fieldsets": [{"fields": [{"name": "P<n>", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "AMCNTENCLR1_EL0", "fullname": "Activity Monitors Count Enable Clear Register 1", "enc": [3, 3, 13, 3, 0], "fieldsets": [{"fields": [{"name": "P<n>", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "AMCNTENSET0_EL0", "fullname": "Activity Monitors Count Enable Set Register 0", "enc": [3, 3, 13, 2, 5], "fieldsets": [{"fields": [{"name": "P<n>", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "AMCNTENSET1_EL0", "fullname": "Activity Monitors Count Enable Set Register 1", "enc": [3, 3, 13, 3, 1], "fieldsets": [{"fields": [{"name": "P<n>", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "AMCR_EL0", "fullname": "Activity Monitors Control Register", "enc": [3, 3, 13, 2, 0], "fieldsets": [{"fields": [{"name": "CG1RZ", "msb": 17, "lsb": 17}, {"name": "HDBG", "msb": 10, "lsb": 10}]}], "width": 64}, {"index": 0, "name": "AMEVCNTR00_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 1, "name": "AMEVCNTR01_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 2, "name": "AMEVCNTR02_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 3, "name": "AMEVCNTR03_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 4, "name": "AMEVCNTR04_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 5, "name": "AMEVCNTR05_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 6, "name": "AMEVCNTR06_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 7, "name": "AMEVCNTR07_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 8, "name": "AMEVCNTR08_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 9, "name": "AMEVCNTR09_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 10, "name": "AMEVCNTR010_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 11, "name": "AMEVCNTR011_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 12, "name": "AMEVCNTR012_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 13, "name": "AMEVCNTR013_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 14, "name": "AMEVCNTR014_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 15, "name": "AMEVCNTR015_EL0", "fullname": "Activity Monitors Event Counter Registers 0", "enc": [3, 3, 13, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AMEVCNTR10_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 1, "name": "AMEVCNTR11_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 2, "name": "AMEVCNTR12_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 3, "name": "AMEVCNTR13_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 4, "name": "AMEVCNTR14_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 5, "name": "AMEVCNTR15_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 6, "name": "AMEVCNTR16_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 7, "name": "AMEVCNTR17_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 8, "name": "AMEVCNTR18_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 9, "name": "AMEVCNTR19_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 10, "name": "AMEVCNTR110_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 11, "name": "AMEVCNTR111_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 12, "name": "AMEVCNTR112_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 13, "name": "AMEVCNTR113_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 14, "name": "AMEVCNTR114_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 15, "name": "AMEVCNTR115_EL0", "fullname": "Activity Monitors Event Counter Registers 1", "enc": [3, 3, 13, 12, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AMEVCNTVOFF00_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 1, "name": "AMEVCNTVOFF01_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 2, "name": "AMEVCNTVOFF02_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 3, "name": "AMEVCNTVOFF03_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 4, "name": "AMEVCNTVOFF04_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 5, "name": "AMEVCNTVOFF05_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 6, "name": "AMEVCNTVOFF06_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 7, "name": "AMEVCNTVOFF07_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 8, "name": "AMEVCNTVOFF08_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 9, "name": "AMEVCNTVOFF09_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 10, "name": "AMEVCNTVOFF010_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 11, "name": "AMEVCNTVOFF011_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 12, "name": "AMEVCNTVOFF012_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 13, "name": "AMEVCNTVOFF013_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 14, "name": "AMEVCNTVOFF014_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 15, "name": "AMEVCNTVOFF015_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 0", "enc": [3, 4, 13, 8, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AMEVCNTVOFF10_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 1, "name": "AMEVCNTVOFF11_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 2, "name": "AMEVCNTVOFF12_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 3, "name": "AMEVCNTVOFF13_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 4, "name": "AMEVCNTVOFF14_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 5, "name": "AMEVCNTVOFF15_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 6, "name": "AMEVCNTVOFF16_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 7, "name": "AMEVCNTVOFF17_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 8, "name": "AMEVCNTVOFF18_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 9, "name": "AMEVCNTVOFF19_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 10, "name": "AMEVCNTVOFF110_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 11, "name": "AMEVCNTVOFF111_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 12, "name": "AMEVCNTVOFF112_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 13, "name": "AMEVCNTVOFF113_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 14, "name": "AMEVCNTVOFF114_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 15, "name": "AMEVCNTVOFF115_EL2", "fullname": "Activity Monitors Event Counter Virtual Offset Registers 1", "enc": [3, 4, 13, 10, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "AMEVTYPER00_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 1, "name": "AMEVTYPER01_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 2, "name": "AMEVTYPER02_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 3, "name": "AMEVTYPER03_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 4, "name": "AMEVTYPER04_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 5, "name": "AMEVTYPER05_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 6, "name": "AMEVTYPER06_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 7, "name": "AMEVTYPER07_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 8, "name": "AMEVTYPER08_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 9, "name": "AMEVTYPER09_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 10, "name": "AMEVTYPER010_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 11, "name": "AMEVTYPER011_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 12, "name": "AMEVTYPER012_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 13, "name": "AMEVTYPER013_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 14, "name": "AMEVTYPER014_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 15, "name": "AMEVTYPER015_EL0", "fullname": "Activity Monitors Event Type Registers 0", "enc": [3, 3, 13, 6, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "AMEVTYPER10_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 1, "name": "AMEVTYPER11_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 2, "name": "AMEVTYPER12_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 3, "name": "AMEVTYPER13_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 4, "name": "AMEVTYPER14_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 5, "name": "AMEVTYPER15_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 6, "name": "AMEVTYPER16_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 7, "name": "AMEVTYPER17_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 8, "name": "AMEVTYPER18_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 9, "name": "AMEVTYPER19_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 10, "name": "AMEVTYPER110_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 11, "name": "AMEVTYPER111_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 12, "name": "AMEVTYPER112_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 13, "name": "AMEVTYPER113_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 14, "name": "AMEVTYPER114_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 15, "name": "AMEVTYPER115_EL0", "fullname": "Activity Monitors Event Type Registers 1", "enc": [3, 3, 13, 14, 0], "fieldsets": [{"fields": [{"name": "evtCount", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "AMUSERENR_EL0", "fullname": "Activity Monitors User Enable Register", "enc": [3, 3, 13, 2, 3], "fieldsets": [{"fields": [{"name": "EN", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "APDAKeyHi_EL1", "fullname": "Pointer Authentication Key A for Data (bits[127:64]) ", "enc": [3, 0, 2, 2, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "APDAKeyLo_EL1", "fullname": "Pointer Authentication Key A for Data (bits[63:0]) ", "enc": [3, 0, 2, 2, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "APDBKeyHi_EL1", "fullname": "Pointer Authentication Key B for Data (bits[127:64]) ", "enc": [3, 0, 2, 2, 3], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "APDBKeyLo_EL1", "fullname": "Pointer Authentication Key B for Data (bits[63:0]) ", "enc": [3, 0, 2, 2, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "APGAKeyHi_EL1", "fullname": "Pointer Authentication Key A for Code (bits[127:64]) ", "enc": [3, 0, 2, 3, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "APGAKeyLo_EL1", "fullname": "Pointer Authentication Key A for Code (bits[63:0]) ", "enc": [3, 0, 2, 3, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "APIAKeyHi_EL1", "fullname": "Pointer Authentication Key A for Instruction (bits[127:64]) ", "enc": [3, 0, 2, 1, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "APIAKeyLo_EL1", "fullname": "Pointer Authentication Key A for Instruction (bits[63:0]) ", "enc": [3, 0, 2, 1, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "APIBKeyHi_EL1", "fullname": "Pointer Authentication Key B for Instruction (bits[127:64]) ", "enc": [3, 0, 2, 1, 3], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "APIBKeyLo_EL1", "fullname": "Pointer Authentication Key B for Instruction (bits[63:0]) ", "enc": [3, 0, 2, 1, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CCSIDR2_EL1", "fullname": "Current Cache Size ID Register 2", "enc": [3, 1, 0, 0, 2], "fieldsets": [{"fields": [{"name": "NumSets", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CCSIDR_EL1", "fullname": "Current Cache Size ID Register", "enc": [3, 1, 0, 0, 0], "fieldsets": [{"instance": "IsFeatureImplemented(FEAT_CCIDX)", "fields": [{"name": "NumSets", "msb": 55, "lsb": 32}, {"name": "Associativity", "msb": 23, "lsb": 3}, {"name": "LineSize", "msb": 2, "lsb": 0}]}, {"instance": "!IsFeatureImplemented(FEAT_CCIDX)", "fields": [{"name": "NumSets", "msb": 27, "lsb": 13}, {"name": "Associativity", "msb": 12, "lsb": 3}, {"name": "LineSize", "msb": 2, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CLIDR_EL1", "fullname": "Cache Level ID Register", "enc": [3, 1, 0, 0, 1], "fieldsets": [{"fields": [{"name": "Ttype<n>", "msb": 46, "lsb": 33}, {"name": "ICB", "msb": 32, "lsb": 30}, {"name": "LoUU", "msb": 29, "lsb": 27}, {"name": "LoC", "msb": 26, "lsb": 24}, {"name": "LoUIS", "msb": 23, "lsb": 21}, {"name": "Ctype<n>", "msb": 20, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTFRQ_EL0", "fullname": "Counter-timer Frequency register", "enc": [3, 3, 14, 0, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTHCTL_EL2", "fullname": "Counter-timer Hypervisor Control register", "enc": [3, 4, 14, 1, 0], "fieldsets": [{"instance": "HCR_EL2.E2H == 1", "fields": [{"name": "EVNTIS", "msb": 17, "lsb": 17}, {"name": "EL1NVVCT", "msb": 16, "lsb": 16}, {"name": "EL1NVPCT", "msb": 15, "lsb": 15}, {"name": "EL1TVCT", "msb": 14, "lsb": 14}, {"name": "EL1TVT", "msb": 13, "lsb": 13}, {"name": "ECV", "msb": 12, "lsb": 12}, {"name": "EL1PTEN", "msb": 11, "lsb": 11}, {"name": "EL1PCTEN", "msb": 10, "lsb": 10}, {"name": "EL0PTEN", "msb": 9, "lsb": 9}, {"name": "EL0VTEN", "msb": 8, "lsb": 8}, {"name": "EVNTI", "msb": 7, "lsb": 4}, {"name": "EVNTDIR", "msb": 3, "lsb": 3}, {"name": "EVNTEN", "msb": 2, "lsb": 2}, {"name": "EL0VCTEN", "msb": 1, "lsb": 1}, {"name": "EL0PCTEN", "msb": 0, "lsb": 0}]}, {"instance": "HCR_EL2.E2H == 0", "fields": [{"name": "EVNTIS", "msb": 17, "lsb": 17}, {"name": "EL1NVVCT", "msb": 16, "lsb": 16}, {"name": "EL1NVPCT", "msb": 15, "lsb": 15}, {"name": "EL1TVCT", "msb": 14, "lsb": 14}, {"name": "EL1TVT", "msb": 13, "lsb": 13}, {"name": "ECV", "msb": 12, "lsb": 12}, {"name": "EVNTI", "msb": 7, "lsb": 4}, {"name": "EVNTDIR", "msb": 3, "lsb": 3}, {"name": "EVNTEN", "msb": 2, "lsb": 2}, {"name": "EL1PCEN", "msb": 1, "lsb": 1}, {"name": "EL1PCTEN", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTKCTL_EL1", "fullname": "Counter-timer Hypervisor Control register", "enc": [3, 0, 14, 1, 0], "fieldsets": [{"instance": "HCR_EL2.E2H == 1", "fields": [{"name": "EVNTIS", "msb": 17, "lsb": 17}, {"name": "EL1NVVCT", "msb": 16, "lsb": 16}, {"name": "EL1NVPCT", "msb": 15, "lsb": 15}, {"name": "EL1TVCT", "msb": 14, "lsb": 14}, {"name": "EL1TVT", "msb": 13, "lsb": 13}, {"name": "ECV", "msb": 12, "lsb": 12}, {"name": "EL1PTEN", "msb": 11, "lsb": 11}, {"name": "EL1PCTEN", "msb": 10, "lsb": 10}, {"name": "EL0PTEN", "msb": 9, "lsb": 9}, {"name": "EL0VTEN", "msb": 8, "lsb": 8}, {"name": "EVNTI", "msb": 7, "lsb": 4}, {"name": "EVNTDIR", "msb": 3, "lsb": 3}, {"name": "EVNTEN", "msb": 2, "lsb": 2}, {"name": "EL0VCTEN", "msb": 1, "lsb": 1}, {"name": "EL0PCTEN", "msb": 0, "lsb": 0}]}, {"instance": "HCR_EL2.E2H == 0", "fields": [{"name": "EVNTIS", "msb": 17, "lsb": 17}, {"name": "EL1NVVCT", "msb": 16, "lsb": 16}, {"name": "EL1NVPCT", "msb": 15, "lsb": 15}, {"name": "EL1TVCT", "msb": 14, "lsb": 14}, {"name": "EL1TVT", "msb": 13, "lsb": 13}, {"name": "ECV", "msb": 12, "lsb": 12}, {"name": "EVNTI", "msb": 7, "lsb": 4}, {"name": "EVNTDIR", "msb": 3, "lsb": 3}, {"name": "EVNTEN", "msb": 2, "lsb": 2}, {"name": "EL1PCEN", "msb": 1, "lsb": 1}, {"name": "EL1PCTEN", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTHP_CTL_EL2", "fullname": "Counter-timer Hypervisor Physical Timer Control register", "enc": [3, 4, 14, 2, 1], "fieldsets": [{"fields": [{"name": "ISTATUS", "msb": 2, "lsb": 2}, {"name": "IMASK", "msb": 1, "lsb": 1}, {"name": "ENABLE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTP_CTL_EL0", "fullname": "Counter-timer Hypervisor Physical Timer Control register", "enc": [3, 3, 14, 2, 1], "fieldsets": [{"fields": [{"name": "ISTATUS", "msb": 2, "lsb": 2}, {"name": "IMASK", "msb": 1, "lsb": 1}, {"name": "ENABLE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTHP_CVAL_EL2", "fullname": "Counter-timer Physical Timer CompareValue register (EL2)", "enc": [3, 4, 14, 2, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTP_CVAL_EL0", "fullname": "Counter-timer Physical Timer CompareValue register (EL2)", "enc": [3, 3, 14, 2, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTHPS_CTL_EL2", "fullname": "Counter-timer Secure Physical Timer Control register (EL2)", "enc": [3, 4, 14, 5, 1], "fieldsets": [{"fields": [{"name": "ISTATUS", "msb": 2, "lsb": 2}, {"name": "IMASK", "msb": 1, "lsb": 1}, {"name": "ENABLE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTP_CTL_EL0", "fullname": "Counter-timer Secure Physical Timer Control register (EL2)", "enc": [3, 3, 14, 2, 1], "fieldsets": [{"fields": [{"name": "ISTATUS", "msb": 2, "lsb": 2}, {"name": "IMASK", "msb": 1, "lsb": 1}, {"name": "ENABLE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTHPS_CVAL_EL2", "fullname": "Counter-timer Secure Physical Timer CompareValue register (EL2)", "enc": [3, 4, 14, 5, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTP_CVAL_EL0", "fullname": "Counter-timer Secure Physical Timer CompareValue register (EL2)", "enc": [3, 3, 14, 2, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTHPS_TVAL_EL2", "fullname": "Counter-timer Secure Physical Timer TimerValue register (EL2)", "enc": [3, 4, 14, 5, 0], "fieldsets": [{"fields": [{"name": "TimerValue", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTP_TVAL_EL0", "fullname": "Counter-timer Secure Physical Timer TimerValue register (EL2)", "enc": [3, 3, 14, 2, 0], "fieldsets": [{"fields": [{"name": "TimerValue", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTHP_TVAL_EL2", "fullname": "Counter-timer Physical Timer TimerValue register (EL2)", "enc": [3, 4, 14, 2, 0], "fieldsets": [{"fields": [{"name": "TimerValue", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTP_TVAL_EL0", "fullname": "Counter-timer Physical Timer TimerValue register (EL2)", "enc": [3, 3, 14, 2, 0], "fieldsets": [{"fields": [{"name": "TimerValue", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTHV_CTL_EL2", "fullname": "Counter-timer Virtual Timer Control register (EL2)", "enc": [3, 4, 14, 3, 1], "fieldsets": [{"fields": [{"name": "ISTATUS", "msb": 2, "lsb": 2}, {"name": "IMASK", "msb": 1, "lsb": 1}, {"name": "ENABLE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTV_CTL_EL0", "fullname": "Counter-timer Virtual Timer Control register (EL2)", "enc": [3, 3, 14, 3, 1], "fieldsets": [{"fields": [{"name": "ISTATUS", "msb": 2, "lsb": 2}, {"name": "IMASK", "msb": 1, "lsb": 1}, {"name": "ENABLE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTHV_CVAL_EL2", "fullname": "Counter-timer Virtual Timer CompareValue register (EL2)", "enc": [3, 4, 14, 3, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTV_CVAL_EL0", "fullname": "Counter-timer Virtual Timer CompareValue register (EL2)", "enc": [3, 3, 14, 3, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTHVS_CTL_EL2", "fullname": "Counter-timer Secure Virtual Timer Control register (EL2)", "enc": [3, 4, 14, 4, 1], "fieldsets": [{"fields": [{"name": "ISTATUS", "msb": 2, "lsb": 2}, {"name": "IMASK", "msb": 1, "lsb": 1}, {"name": "ENABLE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTV_CTL_EL0", "fullname": "Counter-timer Secure Virtual Timer Control register (EL2)", "enc": [3, 3, 14, 3, 1], "fieldsets": [{"fields": [{"name": "ISTATUS", "msb": 2, "lsb": 2}, {"name": "IMASK", "msb": 1, "lsb": 1}, {"name": "ENABLE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTHVS_CVAL_EL2", "fullname": "Counter-timer Secure Virtual Timer CompareValue register (EL2)", "enc": [3, 4, 14, 4, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTV_CVAL_EL0", "fullname": "Counter-timer Secure Virtual Timer CompareValue register (EL2)", "enc": [3, 3, 14, 3, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTHVS_TVAL_EL2", "fullname": "Counter-timer Secure Virtual Timer TimerValue register (EL2)", "enc": [3, 4, 14, 4, 0], "fieldsets": [{"fields": [{"name": "TimerValue", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTV_TVAL_EL0", "fullname": "Counter-timer Secure Virtual Timer TimerValue register (EL2)", "enc": [3, 3, 14, 3, 0], "fieldsets": [{"fields": [{"name": "TimerValue", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTHV_TVAL_EL2", "fullname": "Counter-timer Virtual Timer TimerValue Register (EL2)", "enc": [3, 4, 14, 3, 0], "fieldsets": [{"fields": [{"name": "TimerValue", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTV_TVAL_EL0", "fullname": "Counter-timer Virtual Timer TimerValue Register (EL2)", "enc": [3, 3, 14, 3, 0], "fieldsets": [{"fields": [{"name": "TimerValue", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTKCTL_EL1", "fullname": "Counter-timer Kernel Control register", "enc": [3, 0, 14, 1, 0], "fieldsets": [{"fields": [{"name": "EVNTIS", "msb": 17, "lsb": 17}, {"name": "EL0PTEN", "msb": 9, "lsb": 9}, {"name": "EL0VTEN", "msb": 8, "lsb": 8}, {"name": "EVNTI", "msb": 7, "lsb": 4}, {"name": "EVNTDIR", "msb": 3, "lsb": 3}, {"name": "EVNTEN", "msb": 2, "lsb": 2}, {"name": "EL0VCTEN", "msb": 1, "lsb": 1}, {"name": "EL0PCTEN", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTKCTL_EL12", "fullname": "Counter-timer Kernel Control register", "enc": [3, 5, 14, 1, 0], "fieldsets": [{"fields": [{"name": "EVNTIS", "msb": 17, "lsb": 17}, {"name": "EL0PTEN", "msb": 9, "lsb": 9}, {"name": "EL0VTEN", "msb": 8, "lsb": 8}, {"name": "EVNTI", "msb": 7, "lsb": 4}, {"name": "EVNTDIR", "msb": 3, "lsb": 3}, {"name": "EVNTEN", "msb": 2, "lsb": 2}, {"name": "EL0VCTEN", "msb": 1, "lsb": 1}, {"name": "EL0PCTEN", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTPCT_EL0", "fullname": "Counter-timer Physical Count register", "enc": [3, 3, 14, 0, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTP_CTL_EL0", "fullname": "Counter-timer Physical Timer Control register", "enc": [3, 3, 14, 2, 1], "fieldsets": [{"fields": [{"name": "ISTATUS", "msb": 2, "lsb": 2}, {"name": "IMASK", "msb": 1, "lsb": 1}, {"name": "ENABLE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTP_CTL_EL02", "fullname": "Counter-timer Physical Timer Control register", "enc": [3, 5, 14, 2, 1], "fieldsets": [{"fields": [{"name": "ISTATUS", "msb": 2, "lsb": 2}, {"name": "IMASK", "msb": 1, "lsb": 1}, {"name": "ENABLE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTPCTSS_EL0", "fullname": "Counter-timer Self-Synchronized Physical Count register", "enc": [3, 3, 14, 0, 5], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTP_CVAL_EL0", "fullname": "Counter-timer Physical Timer CompareValue register", "enc": [3, 3, 14, 2, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTP_CVAL_EL02", "fullname": "Counter-timer Physical Timer CompareValue register", "enc": [3, 5, 14, 2, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTPOFF_EL2", "fullname": "Counter-timer Physical Offset register", "enc": [3, 4, 14, 0, 6], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTPS_CTL_EL1", "fullname": "Counter-timer Physical Secure Timer Control register", "enc": [3, 7, 14, 2, 1], "fieldsets": [{"fields": [{"name": "ISTATUS", "msb": 2, "lsb": 2}, {"name": "IMASK", "msb": 1, "lsb": 1}, {"name": "ENABLE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTPS_CVAL_EL1", "fullname": "Counter-timer Physical Secure Timer CompareValue register", "enc": [3, 7, 14, 2, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTPS_TVAL_EL1", "fullname": "Counter-timer Physical Secure Timer TimerValue register", "enc": [3, 7, 14, 2, 0], "fieldsets": [{"fields": [{"name": "TimerValue", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTP_TVAL_EL0", "fullname": "Counter-timer Physical Timer TimerValue register", "enc": [3, 3, 14, 2, 0], "fieldsets": [{"fields": [{"name": "TimerValue", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTP_TVAL_EL02", "fullname": "Counter-timer Physical Timer TimerValue register", "enc": [3, 5, 14, 2, 0], "fieldsets": [{"fields": [{"name": "TimerValue", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTVCT_EL0", "fullname": "Counter-timer Virtual Count register", "enc": [3, 3, 14, 0, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTV_CTL_EL0", "fullname": "Counter-timer Virtual Timer Control register", "enc": [3, 3, 14, 3, 1], "fieldsets": [{"fields": [{"name": "ISTATUS", "msb": 2, "lsb": 2}, {"name": "IMASK", "msb": 1, "lsb": 1}, {"name": "ENABLE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTV_CTL_EL02", "fullname": "Counter-timer Virtual Timer Control register", "enc": [3, 5, 14, 3, 1], "fieldsets": [{"fields": [{"name": "ISTATUS", "msb": 2, "lsb": 2}, {"name": "IMASK", "msb": 1, "lsb": 1}, {"name": "ENABLE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTVCTSS_EL0", "fullname": "Counter-timer Self-Synchronized Virtual Count register", "enc": [3, 3, 14, 0, 6], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTV_CVAL_EL0", "fullname": "Counter-timer Virtual Timer CompareValue register", "enc": [3, 3, 14, 3, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTV_CVAL_EL02", "fullname": "Counter-timer Virtual Timer CompareValue register", "enc": [3, 5, 14, 3, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTVOFF_EL2", "fullname": "Counter-timer Virtual Offset register", "enc": [3, 4, 14, 0, 3], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "CNTV_TVAL_EL0", "fullname": "Counter-timer Virtual Timer TimerValue register", "enc": [3, 3, 14, 3, 0], "fieldsets": [{"fields": [{"name": "TimerValue", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CNTV_TVAL_EL02", "fullname": "Counter-timer Virtual Timer TimerValue register", "enc": [3, 5, 14, 3, 0], "fieldsets": [{"fields": [{"name": "TimerValue", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CONTEXTIDR_EL1", "fullname": "Context ID Register (EL1)", "enc": [3, 0, 13, 0, 1], "fieldsets": [{"fields": [{"name": "PROCID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CONTEXTIDR_EL12", "fullname": "Context ID Register (EL1)", "enc": [3, 5, 13, 0, 1], "fieldsets": [{"fields": [{"name": "PROCID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CONTEXTIDR_EL1", "fullname": "Context ID Register (EL2)", "enc": [3, 0, 13, 0, 1], "fieldsets": [{"fields": [{"name": "PROCID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CONTEXTIDR_EL2", "fullname": "Context ID Register (EL2)", "enc": [3, 4, 13, 0, 1], "fieldsets": [{"fields": [{"name": "PROCID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CPACR_EL1", "fullname": "Architectural Feature Access Control Register", "enc": [3, 0, 1, 0, 2], "fieldsets": [{"fields": [{"name": "TTA", "msb": 28, "lsb": 28}, {"name": "FPEN", "msb": 21, "lsb": 20}, {"name": "ZEN", "msb": 17, "lsb": 16}]}], "width": 64}, {"index": 0, "name": "CPACR_EL12", "fullname": "Architectural Feature Access Control Register", "enc": [3, 5, 1, 0, 2], "fieldsets": [{"fields": [{"name": "TTA", "msb": 28, "lsb": 28}, {"name": "FPEN", "msb": 21, "lsb": 20}, {"name": "ZEN", "msb": 17, "lsb": 16}]}], "width": 64}, {"index": 0, "name": "CPACR_EL1", "fullname": "Architectural Feature Trap Register (EL2)", "enc": [3, 0, 1, 0, 2], "fieldsets": [{"instance": "HCR_EL2.E2H == 1", "fields": [{"name": "TCPAC", "msb": 31, "lsb": 31}, {"name": "TAM", "msb": 30, "lsb": 30}, {"name": "TTA", "msb": 28, "lsb": 28}, {"name": "FPEN", "msb": 21, "lsb": 20}, {"name": "ZEN", "msb": 17, "lsb": 16}]}, {"instance": "HCR_EL2.E2H == 0", "fields": [{"name": "TCPAC", "msb": 31, "lsb": 31}, {"name": "TAM", "msb": 30, "lsb": 30}, {"name": "TTA", "msb": 20, "lsb": 20}, {"name": "TFP", "msb": 10, "lsb": 10}, {"name": "TZ", "msb": 8, "lsb": 8}]}], "width": 64}, {"index": 0, "name": "CPTR_EL2", "fullname": "Architectural Feature Trap Register (EL2)", "enc": [3, 4, 1, 1, 2], "fieldsets": [{"instance": "HCR_EL2.E2H == 1", "fields": [{"name": "TCPAC", "msb": 31, "lsb": 31}, {"name": "TAM", "msb": 30, "lsb": 30}, {"name": "TTA", "msb": 28, "lsb": 28}, {"name": "FPEN", "msb": 21, "lsb": 20}, {"name": "ZEN", "msb": 17, "lsb": 16}]}, {"instance": "HCR_EL2.E2H == 0", "fields": [{"name": "TCPAC", "msb": 31, "lsb": 31}, {"name": "TAM", "msb": 30, "lsb": 30}, {"name": "TTA", "msb": 20, "lsb": 20}, {"name": "TFP", "msb": 10, "lsb": 10}, {"name": "TZ", "msb": 8, "lsb": 8}]}], "width": 64}, {"index": 0, "name": "CPTR_EL3", "fullname": "Architectural Feature Trap Register (EL3)", "enc": [3, 6, 1, 1, 2], "fieldsets": [{"fields": [{"name": "TCPAC", "msb": 31, "lsb": 31}, {"name": "TAM", "msb": 30, "lsb": 30}, {"name": "TTA", "msb": 20, "lsb": 20}, {"name": "TFP", "msb": 10, "lsb": 10}, {"name": "EZ", "msb": 8, "lsb": 8}]}], "width": 64}, {"index": 0, "name": "CSSELR_EL1", "fullname": "Cache Size Selection Register", "enc": [3, 2, 0, 0, 0], "fieldsets": [{"fields": [{"name": "TnD", "msb": 4, "lsb": 4}, {"name": "Level", "msb": 3, "lsb": 1}, {"name": "InD", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CTR_EL0", "fullname": "Cache Type Register", "enc": [3, 3, 0, 0, 1], "fieldsets": [{"fields": [{"name": "TminLine", "msb": 37, "lsb": 32}, {"name": "DIC", "msb": 29, "lsb": 29}, {"name": "IDC", "msb": 28, "lsb": 28}, {"name": "CWG", "msb": 27, "lsb": 24}, {"name": "ERG", "msb": 23, "lsb": 20}, {"name": "DminLine", "msb": 19, "lsb": 16}, {"name": "L1Ip", "msb": 15, "lsb": 14}, {"name": "IminLine", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "CurrentEL", "fullname": "Current Exception Level", "enc": [3, 0, 4, 2, 2], "fieldsets": [{"fields": [{"name": "EL", "msb": 3, "lsb": 2}]}], "width": 64}, {"index": 0, "name": "DACR32_EL2", "fullname": "Domain Access Control Register", "enc": [3, 4, 3, 0, 0], "fieldsets": [{"fields": [{"name": "D<n>", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "DAIF", "fullname": "Interrupt Mask Bits", "enc": [3, 3, 4, 2, 1], "fieldsets": [{"fields": [{"name": "D", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}]}], "width": 64}, {"index": 0, "name": "DBGAUTHSTATUS_EL1", "fullname": "Debug Authentication Status register", "enc": [2, 0, 7, 14, 6], "fieldsets": [{"fields": [{"name": "SNID", "msb": 7, "lsb": 6}, {"name": "SNID", "msb": 7, "lsb": 6}, {"name": "SID", "msb": 5, "lsb": 4}, {"name": "NSNID", "msb": 3, "lsb": 2}, {"name": "NSNID", "msb": 3, "lsb": 2}, {"name": "NSID", "msb": 1, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "DBGBCR0_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 1, "name": "DBGBCR1_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 2, "name": "DBGBCR2_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 3, "name": "DBGBCR3_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 4, "name": "DBGBCR4_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 5, "name": "DBGBCR5_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 6, "name": "DBGBCR6_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 7, "name": "DBGBCR7_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 8, "name": "DBGBCR8_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 9, "name": "DBGBCR9_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 10, "name": "DBGBCR10_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 11, "name": "DBGBCR11_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 12, "name": "DBGBCR12_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 13, "name": "DBGBCR13_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 14, "name": "DBGBCR14_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 15, "name": "DBGBCR15_EL1", "fullname": "Debug Breakpoint Control Registers", "enc": [2, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "BT", "msb": 23, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 8, "lsb": 5}, {"name": "PMC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "DBGBVR0_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 1, "name": "DBGBVR1_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 2, "name": "DBGBVR2_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 3, "name": "DBGBVR3_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 4, "name": "DBGBVR4_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 5, "name": "DBGBVR5_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 6, "name": "DBGBVR6_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 7, "name": "DBGBVR7_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 8, "name": "DBGBVR8_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 9, "name": "DBGBVR9_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 10, "name": "DBGBVR10_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 11, "name": "DBGBVR11_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 12, "name": "DBGBVR12_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 13, "name": "DBGBVR13_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 14, "name": "DBGBVR14_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 15, "name": "DBGBVR15_EL1", "fullname": "Debug Breakpoint Value Registers", "enc": [2, 0, 0, 0, 4], "fieldsets": [{"instance": "DBGBCR<n>_EL1.BT==0b000x", "fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}, {"instance": "DBGBCR<n>_EL1.BT==0b001x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b011x", "fields": [{"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b100x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b101x and EL2 implemented", "fields": [{"name": "VMID[15:8]", "msb": 47, "lsb": 40}, {"name": "VMID[7:0]", "msb": 39, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}, {"instance": "DBGBCR<n>_EL1.BT==0b110x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}]}, {"instance": "DBGBCR<n>_EL1.BT==0b111x, EL2 implemented, and (FEAT_VHE implemented or FEAT_Debugv8p2 implemented)", "fields": [{"name": "ContextID2", "msb": 63, "lsb": 32}, {"name": "ContextID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "DBGCLAIMCLR_EL1", "fullname": "Debug CLAIM Tag Clear register", "enc": [2, 0, 7, 9, 6], "fieldsets": [{"fields": [{"name": "CLAIM", "msb": 7, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "DBGCLAIMSET_EL1", "fullname": "Debug CLAIM Tag Set register", "enc": [2, 0, 7, 8, 6], "fieldsets": [{"fields": [{"name": "CLAIM", "msb": 7, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "DBGDTR_EL0", "fullname": "Debug Data Transfer Register, half-duplex", "enc": [2, 3, 0, 4, 0], "fieldsets": [{"fields": [{"name": "HighWord", "msb": 63, "lsb": 32}, {"name": "LowWord", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "DBGDTRRX_EL0", "fullname": "Debug Data Transfer Register, Receive", "enc": [2, 3, 0, 5, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "DBGDTRTX_EL0", "fullname": "Debug Data Transfer Register, Transmit", "enc": [2, 3, 0, 5, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "DBGPRCR_EL1", "fullname": "Debug Power Control Register", "enc": [2, 0, 1, 4, 4], "fieldsets": [{"fields": [{"name": "CORENPDRQ", "msb": 0, "lsb": 0}, {"name": "CORENPDRQ", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "DBGVCR32_EL2", "fullname": "Debug Vector Catch Register", "enc": [2, 4, 0, 7, 0], "fieldsets": [{"instance": "EL3 implemented and using AArch64", "fields": [{"name": "NSF", "msb": 31, "lsb": 31}, {"name": "NSI", "msb": 30, "lsb": 30}, {"name": "NSD", "msb": 28, "lsb": 28}, {"name": "NSP", "msb": 27, "lsb": 27}, {"name": "NSS", "msb": 26, "lsb": 26}, {"name": "NSU", "msb": 25, "lsb": 25}, {"name": "SF", "msb": 7, "lsb": 7}, {"name": "SI", "msb": 6, "lsb": 6}, {"name": "SD", "msb": 4, "lsb": 4}, {"name": "SP", "msb": 3, "lsb": 3}, {"name": "SS", "msb": 2, "lsb": 2}, {"name": "SU", "msb": 1, "lsb": 1}]}, {"instance": "EL3 not implemented", "fields": [{"name": "F", "msb": 7, "lsb": 7}, {"name": "I", "msb": 6, "lsb": 6}, {"name": "D", "msb": 4, "lsb": 4}, {"name": "P", "msb": 3, "lsb": 3}, {"name": "S", "msb": 2, "lsb": 2}, {"name": "U", "msb": 1, "lsb": 1}]}], "width": 64}, {"index": 0, "name": "DBGWCR0_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 1, "name": "DBGWCR1_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 2, "name": "DBGWCR2_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 3, "name": "DBGWCR3_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 4, "name": "DBGWCR4_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 5, "name": "DBGWCR5_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 6, "name": "DBGWCR6_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 7, "name": "DBGWCR7_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 8, "name": "DBGWCR8_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 9, "name": "DBGWCR9_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 10, "name": "DBGWCR10_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 11, "name": "DBGWCR11_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 12, "name": "DBGWCR12_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 13, "name": "DBGWCR13_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 14, "name": "DBGWCR14_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 15, "name": "DBGWCR15_EL1", "fullname": "Debug Watchpoint Control Registers", "enc": [2, 0, 0, 0, 7], "fieldsets": [{"fields": [{"name": "MASK", "msb": 28, "lsb": 24}, {"name": "WT", "msb": 20, "lsb": 20}, {"name": "LBN", "msb": 19, "lsb": 16}, {"name": "SSC", "msb": 15, "lsb": 14}, {"name": "HMC", "msb": 13, "lsb": 13}, {"name": "BAS", "msb": 12, "lsb": 5}, {"name": "LSC", "msb": 4, "lsb": 3}, {"name": "PAC", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "DBGWVR0_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 1, "name": "DBGWVR1_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 2, "name": "DBGWVR2_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 3, "name": "DBGWVR3_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 4, "name": "DBGWVR4_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 5, "name": "DBGWVR5_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 6, "name": "DBGWVR6_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 7, "name": "DBGWVR7_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 8, "name": "DBGWVR8_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 9, "name": "DBGWVR9_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 10, "name": "DBGWVR10_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 11, "name": "DBGWVR11_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 12, "name": "DBGWVR12_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 13, "name": "DBGWVR13_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 14, "name": "DBGWVR14_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 15, "name": "DBGWVR15_EL1", "fullname": "Debug Watchpoint Value Registers", "enc": [2, 0, 0, 0, 6], "fieldsets": [{"fields": [{"name": "RESS[14:4]", "msb": 63, "lsb": 53}, {"name": "VA[52:49]", "msb": 52, "lsb": 49}, {"name": "RESS[3:0]", "msb": 52, "lsb": 49}, {"name": "VA[48:2]", "msb": 48, "lsb": 2}]}], "width": 64}, {"index": 0, "name": "DCZID_EL0", "fullname": "Data Cache Zero ID register", "enc": [3, 3, 0, 0, 7], "fieldsets": [{"fields": [{"name": "DZP", "msb": 4, "lsb": 4}, {"name": "BS", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "DISR_EL1", "fullname": "Deferred Interrupt Status Register", "enc": [3, 0, 12, 1, 1], "fieldsets": [{"fields": [{"name": "A", "msb": 31, "lsb": 31}, {"name": "IDS", "msb": 24, "lsb": 24}, {"name": "AET", "msb": 12, "lsb": 10}, {"name": "EA", "msb": 9, "lsb": 9}, {"name": "DFSC", "msb": 5, "lsb": 0}]}, {"fields": [{"name": "A", "msb": 31, "lsb": 31}, {"name": "IDS", "msb": 24, "lsb": 24}, {"name": "ISS", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "DIT", "fullname": "Data Independent Timing", "enc": [3, 3, 4, 2, 5], "fieldsets": [{"fields": [{"name": "DIT", "msb": 24, "lsb": 24}]}], "width": 64}, {"index": 0, "name": "DLR_EL0", "fullname": "Debug Link Register", "enc": [3, 3, 4, 5, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "DSPSR_EL0", "fullname": "Debug Saved Program Status Register", "enc": [3, 3, 4, 5, 0], "fieldsets": [{"instance": "exiting Debug state to AArch32 state", "fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "Q", "msb": 27, "lsb": 27}, {"name": "IT", "msb": 26, "lsb": 25}, {"name": "DIT", "msb": 24, "lsb": 24}, {"name": "SSBS", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "SS", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "GE", "msb": 19, "lsb": 16}, {"name": "IT[7:2]", "msb": 15, "lsb": 10}, {"name": "E", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "T", "msb": 5, "lsb": 5}, {"name": "M[4]", "msb": 4, "lsb": 4}, {"name": "M[3:0]", "msb": 3, "lsb": 0}]}, {"instance": "entering or exiting Debug state from or to AArch64 state", "fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "TCO", "msb": 25, "lsb": 25}, {"name": "DIT", "msb": 24, "lsb": 24}, {"name": "UAO", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "SS", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "SSBS", "msb": 12, "lsb": 12}, {"name": "BTYPE", "msb": 11, "lsb": 10}, {"name": "D", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "M[4]", "msb": 4, "lsb": 4}, {"name": "M[3:0]", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ELR_EL1", "fullname": "Exception Link Register (EL1)", "enc": [3, 0, 4, 0, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "ELR_EL12", "fullname": "Exception Link Register (EL1)", "enc": [3, 5, 4, 0, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "ELR_EL2", "fullname": "Exception Link Register (EL1)", "enc": [3, 4, 4, 0, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "ELR_EL1", "fullname": "Exception Link Register (EL2)", "enc": [3, 0, 4, 0, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "ELR_EL2", "fullname": "Exception Link Register (EL2)", "enc": [3, 4, 4, 0, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "ELR_EL3", "fullname": "Exception Link Register (EL3)", "enc": [3, 6, 4, 0, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "ERRIDR_EL1", "fullname": "Error Record ID Register", "enc": [3, 0, 5, 3, 0], "fieldsets": [{"instance": "ERRIDR_EL1", "fields": [{"name": "NUM", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ERRSELR_EL1", "fullname": "Error Record Select Register", "enc": [3, 0, 5, 3, 1], "fieldsets": [{"instance": "ERRSELR_EL1", "fields": [{"name": "SEL", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ERXADDR_EL1", "fullname": "Selected Error Record Address Register", "enc": [3, 0, 5, 4, 3], "fieldsets": [{"instance": "ERXADDR_EL1", "fields": []}], "width": 64}, {"index": 0, "name": "ERXCTLR_EL1", "fullname": "Selected Error Record Control Register", "enc": [3, 0, 5, 4, 1], "fieldsets": [{"instance": "ERXCTLR_EL1", "fields": []}], "width": 64}, {"index": 0, "name": "ERXFR_EL1", "fullname": "Selected Error Record Feature Register", "enc": [3, 0, 5, 4, 0], "fieldsets": [{"instance": "ERXFR_EL1", "fields": []}], "width": 64}, {"index": 0, "name": "ERXMISC0_EL1", "fullname": "Selected Error Record Miscellaneous Register 0", "enc": [3, 0, 5, 5, 0], "fieldsets": [{"instance": "ERXMISC0_EL1", "fields": []}], "width": 64}, {"index": 0, "name": "ERXMISC1_EL1", "fullname": "Selected Error Record Miscellaneous Register 1", "enc": [3, 0, 5, 5, 1], "fieldsets": [{"instance": "ERXMISC1_EL1", "fields": []}], "width": 64}, {"index": 0, "name": "ERXMISC2_EL1", "fullname": "Selected Error Record Miscellaneous Register 2", "enc": [3, 0, 5, 5, 2], "fieldsets": [{"instance": "ERXMISC2_EL1", "fields": []}], "width": 64}, {"index": 0, "name": "ERXMISC3_EL1", "fullname": "Selected Error Record Miscellaneous Register 3", "enc": [3, 0, 5, 5, 3], "fieldsets": [{"instance": "ERXMISC3_EL1", "fields": []}], "width": 64}, {"index": 0, "name": "ERXPFGCDN_EL1", "fullname": "Selected Pseudo-fault Generation Countdown register", "enc": [3, 0, 5, 4, 6], "fieldsets": [{"instance": "ERXPFGCDN_EL1", "fields": []}], "width": 64}, {"index": 0, "name": "ERXPFGCTL_EL1", "fullname": "Selected Pseudo-fault Generation Control register", "enc": [3, 0, 5, 4, 5], "fieldsets": [{"instance": "ERXPFGCTL_EL1", "fields": []}], "width": 64}, {"index": 0, "name": "ERXPFGF_EL1", "fullname": "Selected Pseudo-fault Generation Feature register", "enc": [3, 0, 5, 4, 4], "fieldsets": [{"instance": "ERXPFGF_EL1", "fields": []}], "width": 64}, {"index": 0, "name": "ERXSTATUS_EL1", "fullname": "Selected Error Record Primary Status Register", "enc": [3, 0, 5, 4, 2], "fieldsets": [{"instance": "ERXSTATUS_EL1", "fields": []}], "width": 64}, {"index": 0, "name": "ESR_EL1", "fullname": "Exception Syndrome Register (EL1)", "enc": [3, 0, 5, 2, 0], "fieldsets": [{"fields": [{"name": "ISS2", "msb": 36, "lsb": 32}, {"name": "EC", "msb": 31, "lsb": 26}, {"name": "IL", "msb": 25, "lsb": 25}, {"name": "ISS", "msb": 24, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ESR_EL12", "fullname": "Exception Syndrome Register (EL1)", "enc": [3, 5, 5, 2, 0], "fieldsets": [{"fields": [{"name": "ISS2", "msb": 36, "lsb": 32}, {"name": "EC", "msb": 31, "lsb": 26}, {"name": "IL", "msb": 25, "lsb": 25}, {"name": "ISS", "msb": 24, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ESR_EL2", "fullname": "Exception Syndrome Register (EL1)", "enc": [3, 4, 5, 2, 0], "fieldsets": [{"fields": [{"name": "ISS2", "msb": 36, "lsb": 32}, {"name": "EC", "msb": 31, "lsb": 26}, {"name": "IL", "msb": 25, "lsb": 25}, {"name": "ISS", "msb": 24, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ESR_EL1", "fullname": "Exception Syndrome Register (EL2)", "enc": [3, 0, 5, 2, 0], "fieldsets": [{"fields": [{"name": "ISS2", "msb": 36, "lsb": 32}, {"name": "EC", "msb": 31, "lsb": 26}, {"name": "IL", "msb": 25, "lsb": 25}, {"name": "ISS", "msb": 24, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ESR_EL2", "fullname": "Exception Syndrome Register (EL2)", "enc": [3, 4, 5, 2, 0], "fieldsets": [{"fields": [{"name": "ISS2", "msb": 36, "lsb": 32}, {"name": "EC", "msb": 31, "lsb": 26}, {"name": "IL", "msb": 25, "lsb": 25}, {"name": "ISS", "msb": 24, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ESR_EL3", "fullname": "Exception Syndrome Register (EL3)", "enc": [3, 6, 5, 2, 0], "fieldsets": [{"fields": [{"name": "ISS2", "msb": 36, "lsb": 32}, {"name": "EC", "msb": 31, "lsb": 26}, {"name": "IL", "msb": 25, "lsb": 25}, {"name": "ISS", "msb": 24, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "FAR_EL1", "fullname": "Fault Address Register (EL1)", "enc": [3, 0, 6, 0, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "FAR_EL12", "fullname": "Fault Address Register (EL1)", "enc": [3, 5, 6, 0, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "FAR_EL2", "fullname": "Fault Address Register (EL1)", "enc": [3, 4, 6, 0, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "FAR_EL1", "fullname": "Fault Address Register (EL2)", "enc": [3, 0, 6, 0, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "FAR_EL2", "fullname": "Fault Address Register (EL2)", "enc": [3, 4, 6, 0, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "FAR_EL3", "fullname": "Fault Address Register (EL3)", "enc": [3, 6, 6, 0, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "FPCR", "fullname": "Floating-point Control Register", "enc": [3, 3, 4, 4, 0], "fieldsets": [{"fields": [{"name": "AHP", "msb": 26, "lsb": 26}, {"name": "DN", "msb": 25, "lsb": 25}, {"name": "FZ", "msb": 24, "lsb": 24}, {"name": "RMode", "msb": 23, "lsb": 22}, {"name": "Stride", "msb": 21, "lsb": 20}, {"name": "FZ16", "msb": 19, "lsb": 19}, {"name": "Len", "msb": 18, "lsb": 16}, {"name": "IDE", "msb": 15, "lsb": 15}, {"name": "IXE", "msb": 12, "lsb": 12}, {"name": "UFE", "msb": 11, "lsb": 11}, {"name": "OFE", "msb": 10, "lsb": 10}, {"name": "DZE", "msb": 9, "lsb": 9}, {"name": "IOE", "msb": 8, "lsb": 8}, {"name": "NEP", "msb": 2, "lsb": 2}, {"name": "AH", "msb": 1, "lsb": 1}, {"name": "FIZ", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "FPEXC32_EL2", "fullname": "Floating-Point Exception Control register", "enc": [3, 4, 5, 3, 0], "fieldsets": [{"fields": [{"name": "EX", "msb": 31, "lsb": 31}, {"name": "EN", "msb": 30, "lsb": 30}, {"name": "DEX", "msb": 29, "lsb": 29}, {"name": "FP2V", "msb": 28, "lsb": 28}, {"name": "VV", "msb": 27, "lsb": 27}, {"name": "TFV", "msb": 26, "lsb": 26}, {"name": "VECITR", "msb": 10, "lsb": 8}, {"name": "IDF", "msb": 7, "lsb": 7}, {"name": "IXF", "msb": 4, "lsb": 4}, {"name": "UFF", "msb": 3, "lsb": 3}, {"name": "OFF", "msb": 2, "lsb": 2}, {"name": "DZF", "msb": 1, "lsb": 1}, {"name": "IOF", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "FPSR", "fullname": "Floating-point Status Register", "enc": [3, 3, 4, 4, 1], "fieldsets": [{"fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "QC", "msb": 27, "lsb": 27}, {"name": "IDC", "msb": 7, "lsb": 7}, {"name": "IXC", "msb": 4, "lsb": 4}, {"name": "UFC", "msb": 3, "lsb": 3}, {"name": "OFC", "msb": 2, "lsb": 2}, {"name": "DZC", "msb": 1, "lsb": 1}, {"name": "IOC", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "GCR_EL1", "fullname": "Tag Control Register.", "enc": [3, 0, 1, 0, 6], "fieldsets": [{"fields": [{"name": "RRND", "msb": 16, "lsb": 16}, {"name": "Exclude", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "GMID_EL1", "fullname": " Multiple tag transfer ID register", "enc": [3, 1, 0, 0, 4], "fieldsets": [{"fields": [{"name": "BS", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "HACR_EL2", "fullname": "Hypervisor Auxiliary Control Register", "enc": [3, 4, 1, 1, 7], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "HAFGRTR_EL2", "fullname": "Hypervisor Activity Monitors Fine-Grained Read Trap Register", "enc": [3, 4, 3, 1, 6], "fieldsets": [{"instance": "HAFGRTR_EL2", "fields": [{"name": "AMEVTYPER1<x>_EL0", "msb": 49, "lsb": 49}, {"name": "AMEVTYPER115_EL0", "msb": 49, "lsb": 49}, {"name": "AMEVCNTR1<x>_EL0", "msb": 48, "lsb": 48}, {"name": "AMEVCNTR115_EL0", "msb": 48, "lsb": 48}, {"name": "AMEVTYPER114_EL0", "msb": 47, "lsb": 47}, {"name": "AMEVCNTR114_EL0", "msb": 46, "lsb": 46}, {"name": "AMEVTYPER113_EL0", "msb": 45, "lsb": 45}, {"name": "AMEVCNTR113_EL0", "msb": 44, "lsb": 44}, {"name": "AMEVTYPER112_EL0", "msb": 43, "lsb": 43}, {"name": "AMEVCNTR112_EL0", "msb": 42, "lsb": 42}, {"name": "AMEVTYPER111_EL0", "msb": 41, "lsb": 41}, {"name": "AMEVCNTR111_EL0", "msb": 40, "lsb": 40}, {"name": "AMEVTYPER110_EL0", "msb": 39, "lsb": 39}, {"name": "AMEVCNTR110_EL0", "msb": 38, "lsb": 38}, {"name": "AMEVTYPER19_EL0", "msb": 37, "lsb": 37}, {"name": "AMEVCNTR19_EL0", "msb": 36, "lsb": 36}, {"name": "AMEVTYPER18_EL0", "msb": 35, "lsb": 35}, {"name": "AMEVCNTR18_EL0", "msb": 34, "lsb": 34}, {"name": "AMEVTYPER17_EL0", "msb": 33, "lsb": 33}, {"name": "AMEVCNTR17_EL0", "msb": 32, "lsb": 32}, {"name": "AMEVTYPER16_EL0", "msb": 31, "lsb": 31}, {"name": "AMEVCNTR16_EL0", "msb": 30, "lsb": 30}, {"name": "AMEVTYPER15_EL0", "msb": 29, "lsb": 29}, {"name": "AMEVCNTR15_EL0", "msb": 28, "lsb": 28}, {"name": "AMEVTYPER14_EL0", "msb": 27, "lsb": 27}, {"name": "AMEVCNTR14_EL0", "msb": 26, "lsb": 26}, {"name": "AMEVTYPER13_EL0", "msb": 25, "lsb": 25}, {"name": "AMEVCNTR13_EL0", "msb": 24, "lsb": 24}, {"name": "AMEVTYPER12_EL0", "msb": 23, "lsb": 23}, {"name": "AMEVCNTR12_EL0", "msb": 22, "lsb": 22}, {"name": "AMEVTYPER11_EL0", "msb": 21, "lsb": 21}, {"name": "AMEVCNTR11_EL0", "msb": 20, "lsb": 20}, {"name": "AMEVTYPER10_EL0", "msb": 19, "lsb": 19}, {"name": "AMEVCNTR10_EL0", "msb": 18, "lsb": 18}, {"name": "AMCNTEN<x>", "msb": 17, "lsb": 17}, {"name": "AMCNTEN1", "msb": 17, "lsb": 17}, {"name": "AMEVCNTR0<x>_EL0", "msb": 4, "lsb": 1}, {"name": "AMCNTEN0", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "HCR_EL2", "fullname": "Hypervisor Configuration Register", "enc": [3, 4, 1, 1, 0], "fieldsets": [{"fields": [{"name": "TWEDEL", "msb": 63, "lsb": 60}, {"name": "TWEDEn", "msb": 59, "lsb": 59}, {"name": "TID5", "msb": 58, "lsb": 58}, {"name": "DCT", "msb": 57, "lsb": 57}, {"name": "ATA", "msb": 56, "lsb": 56}, {"name": "TTLBOS", "msb": 55, "lsb": 55}, {"name": "TTLBIS", "msb": 54, "lsb": 54}, {"name": "EnSCXT", "msb": 53, "lsb": 53}, {"name": "TOCU", "msb": 52, "lsb": 52}, {"name": "AMVOFFEN", "msb": 51, "lsb": 51}, {"name": "TICAB", "msb": 50, "lsb": 50}, {"name": "TID4", "msb": 49, "lsb": 49}, {"name": "FIEN", "msb": 47, "lsb": 47}, {"name": "FWB", "msb": 46, "lsb": 46}, {"name": "NV2", "msb": 45, "lsb": 45}, {"name": "AT", "msb": 44, "lsb": 44}, {"name": "NV1", "msb": 43, "lsb": 43}, {"name": "NV1", "msb": 43, "lsb": 43}, {"name": "NV", "msb": 42, "lsb": 42}, {"name": "NV", "msb": 42, "lsb": 42}, {"name": "API", "msb": 41, "lsb": 41}, {"name": "APK", "msb": 40, "lsb": 40}, {"name": "MIOCNCE", "msb": 38, "lsb": 38}, {"name": "TEA", "msb": 37, "lsb": 37}, {"name": "TERR", "msb": 36, "lsb": 36}, {"name": "TLOR", "msb": 35, "lsb": 35}, {"name": "E2H", "msb": 34, "lsb": 34}, {"name": "ID", "msb": 33, "lsb": 33}, {"name": "CD", "msb": 32, "lsb": 32}, {"name": "RW", "msb": 31, "lsb": 31}, {"name": "TRVM", "msb": 30, "lsb": 30}, {"name": "HCD", "msb": 29, "lsb": 29}, {"name": "TDZ", "msb": 28, "lsb": 28}, {"name": "TGE", "msb": 27, "lsb": 27}, {"name": "TVM", "msb": 26, "lsb": 26}, {"name": "TTLB", "msb": 25, "lsb": 25}, {"name": "TPU", "msb": 24, "lsb": 24}, {"name": "TPCP", "msb": 23, "lsb": 23}, {"name": "TPC", "msb": 23, "lsb": 23}, {"name": "TSW", "msb": 22, "lsb": 22}, {"name": "TACR", "msb": 21, "lsb": 21}, {"name": "TIDCP", "msb": 20, "lsb": 20}, {"name": "TSC", "msb": 19, "lsb": 19}, {"name": "TID3", "msb": 18, "lsb": 18}, {"name": "TID2", "msb": 17, "lsb": 17}, {"name": "TID1", "msb": 16, "lsb": 16}, {"name": "TID0", "msb": 15, "lsb": 15}, {"name": "TWE", "msb": 14, "lsb": 14}, {"name": "TWI", "msb": 13, "lsb": 13}, {"name": "DC", "msb": 12, "lsb": 12}, {"name": "BSU", "msb": 11, "lsb": 10}, {"name": "FB", "msb": 9, "lsb": 9}, {"name": "VSE", "msb": 8, "lsb": 8}, {"name": "VI", "msb": 7, "lsb": 7}, {"name": "VF", "msb": 6, "lsb": 6}, {"name": "AMO", "msb": 5, "lsb": 5}, {"name": "IMO", "msb": 4, "lsb": 4}, {"name": "FMO", "msb": 3, "lsb": 3}, {"name": "PTW", "msb": 2, "lsb": 2}, {"name": "SWIO", "msb": 1, "lsb": 1}, {"name": "VM", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "HCRX_EL2", "fullname": "Extended Hypervisor Configuration Register", "enc": [3, 4, 1, 2, 2], "fieldsets": [{"fields": [{"name": "FGTnXS", "msb": 4, "lsb": 4}, {"name": "FnXS", "msb": 3, "lsb": 3}, {"name": "EnASR", "msb": 2, "lsb": 2}, {"name": "EnALS", "msb": 1, "lsb": 1}, {"name": "EnAS0", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "HDFGRTR_EL2", "fullname": "Hypervisor Debug Fine-Grained Read Trap Register", "enc": [3, 4, 3, 1, 4], "fieldsets": [{"instance": "HDFGRTR_EL2", "fields": [{"name": "nPMSNEVFR_EL1", "msb": 62, "lsb": 62}, {"name": "PMCEIDn_EL0", "msb": 58, "lsb": 58}, {"name": "PMUSERENR_EL0", "msb": 57, "lsb": 57}, {"name": "TRCVICTLR", "msb": 48, "lsb": 48}, {"name": "TRCSTATR", "msb": 47, "lsb": 47}, {"name": "TRCSSCSRn", "msb": 46, "lsb": 46}, {"name": "TRCSEQSTR", "msb": 45, "lsb": 45}, {"name": "TRCPRGCTLR", "msb": 44, "lsb": 44}, {"name": "TRCOSLSR", "msb": 43, "lsb": 43}, {"name": "TRCIMSPECn", "msb": 41, "lsb": 41}, {"name": "TRCID", "msb": 40, "lsb": 40}, {"name": "TRCCNTVRn", "msb": 37, "lsb": 37}, {"name": "TRCCLAIM", "msb": 36, "lsb": 36}, {"name": "TRCAUXCTLR", "msb": 35, "lsb": 35}, {"name": "TRCAUTHSTATUS", "msb": 34, "lsb": 34}, {"name": "TRC", "msb": 33, "lsb": 33}, {"name": "PMSLATFR_EL1", "msb": 32, "lsb": 32}, {"name": "PMSIRR_EL1", "msb": 31, "lsb": 31}, {"name": "PMSIDR_EL1", "msb": 30, "lsb": 30}, {"name": "PMSICR_EL1", "msb": 29, "lsb": 29}, {"name": "PMSFCR_EL1", "msb": 28, "lsb": 28}, {"name": "PMSEVFR_EL1", "msb": 27, "lsb": 27}, {"name": "PMSCR_EL1", "msb": 26, "lsb": 26}, {"name": "PMBSR_EL1", "msb": 25, "lsb": 25}, {"name": "PMBPTR_EL1", "msb": 24, "lsb": 24}, {"name": "PMBLIMITR_EL1", "msb": 23, "lsb": 23}, {"name": "PMMIR_EL1", "msb": 22, "lsb": 22}, {"name": "PMSELR_EL0", "msb": 19, "lsb": 19}, {"name": "PMOVS", "msb": 18, "lsb": 18}, {"name": "PMINTEN", "msb": 17, "lsb": 17}, {"name": "PMCNTEN", "msb": 16, "lsb": 16}, {"name": "PMCCNTR_EL0", "msb": 15, "lsb": 15}, {"name": "PMCCFILTR_EL0", "msb": 14, "lsb": 14}, {"name": "PMEVTYPERn_EL0", "msb": 13, "lsb": 13}, {"name": "PMEVCNTRn_EL0", "msb": 12, "lsb": 12}, {"name": "OSDLR_EL1", "msb": 11, "lsb": 11}, {"name": "OSECCR_EL1", "msb": 10, "lsb": 10}, {"name": "OSLSR_EL1", "msb": 9, "lsb": 9}, {"name": "DBGPRCR_EL1", "msb": 7, "lsb": 7}, {"name": "DBGAUTHSTATUS_EL1", "msb": 6, "lsb": 6}, {"name": "DBGCLAIM", "msb": 5, "lsb": 5}, {"name": "MDSCR_EL1", "msb": 4, "lsb": 4}, {"name": "DBGWVRn_EL1", "msb": 3, "lsb": 3}, {"name": "DBGWCRn_EL1", "msb": 2, "lsb": 2}, {"name": "DBGBVRn_EL1", "msb": 1, "lsb": 1}, {"name": "DBGBCRn_EL1", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "HDFGWTR_EL2", "fullname": "Hypervisor Debug Fine-Grained Write Trap Register", "enc": [3, 4, 3, 1, 5], "fieldsets": [{"instance": "HDFGWTR_EL2", "fields": [{"name": "nPMSNEVFR_EL1", "msb": 62, "lsb": 62}, {"name": "PMUSERENR_EL0", "msb": 57, "lsb": 57}, {"name": "TRFCR_EL1", "msb": 49, "lsb": 49}, {"name": "TRCVICTLR", "msb": 48, "lsb": 48}, {"name": "TRCSSCSRn", "msb": 46, "lsb": 46}, {"name": "TRCSEQSTR", "msb": 45, "lsb": 45}, {"name": "TRCPRGCTLR", "msb": 44, "lsb": 44}, {"name": "TRCOSLAR", "msb": 42, "lsb": 42}, {"name": "TRCIMSPECn", "msb": 41, "lsb": 41}, {"name": "TRCCNTVRn", "msb": 37, "lsb": 37}, {"name": "TRCCLAIM", "msb": 36, "lsb": 36}, {"name": "TRCAUXCTLR", "msb": 35, "lsb": 35}, {"name": "TRC", "msb": 33, "lsb": 33}, {"name": "PMSLATFR_EL1", "msb": 32, "lsb": 32}, {"name": "PMSIRR_EL1", "msb": 31, "lsb": 31}, {"name": "PMSICR_EL1", "msb": 29, "lsb": 29}, {"name": "PMSFCR_EL1", "msb": 28, "lsb": 28}, {"name": "PMSEVFR_EL1", "msb": 27, "lsb": 27}, {"name": "PMSCR_EL1", "msb": 26, "lsb": 26}, {"name": "PMBSR_EL1", "msb": 25, "lsb": 25}, {"name": "PMBPTR_EL1", "msb": 24, "lsb": 24}, {"name": "PMBLIMITR_EL1", "msb": 23, "lsb": 23}, {"name": "PMCR_EL0", "msb": 21, "lsb": 21}, {"name": "PMSWINC_EL0", "msb": 20, "lsb": 20}, {"name": "PMSELR_EL0", "msb": 19, "lsb": 19}, {"name": "PMOVS", "msb": 18, "lsb": 18}, {"name": "PMINTEN", "msb": 17, "lsb": 17}, {"name": "PMCNTEN", "msb": 16, "lsb": 16}, {"name": "PMCCNTR_EL0", "msb": 15, "lsb": 15}, {"name": "PMCCFILTR_EL0", "msb": 14, "lsb": 14}, {"name": "PMEVTYPERn_EL0", "msb": 13, "lsb": 13}, {"name": "PMEVCNTRn_EL0", "msb": 12, "lsb": 12}, {"name": "OSDLR_EL1", "msb": 11, "lsb": 11}, {"name": "OSECCR_EL1", "msb": 10, "lsb": 10}, {"name": "OSLAR_EL1", "msb": 8, "lsb": 8}, {"name": "DBGPRCR_EL1", "msb": 7, "lsb": 7}, {"name": "DBGCLAIM", "msb": 5, "lsb": 5}, {"name": "MDSCR_EL1", "msb": 4, "lsb": 4}, {"name": "DBGWVRn_EL1", "msb": 3, "lsb": 3}, {"name": "DBGWCRn_EL1", "msb": 2, "lsb": 2}, {"name": "DBGBVRn_EL1", "msb": 1, "lsb": 1}, {"name": "DBGBCRn_EL1", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "HFGITR_EL2", "fullname": "Hypervisor Fine-Grained Instruction Trap Register", "enc": [3, 4, 1, 1, 6], "fieldsets": [{"instance": "HFGITR_EL2", "fields": [{"name": "DCCVAC", "msb": 54, "lsb": 54}, {"name": "SVC_EL1", "msb": 53, "lsb": 53}, {"name": "SVC_EL0", "msb": 52, "lsb": 52}, {"name": "ERET", "msb": 51, "lsb": 51}, {"name": "CPPRCTX", "msb": 50, "lsb": 50}, {"name": "DVPRCTX", "msb": 49, "lsb": 49}, {"name": "CFPRCTX", "msb": 48, "lsb": 48}, {"name": "TLBIVAALE1", "msb": 47, "lsb": 47}, {"name": "TLBIVALE1", "msb": 46, "lsb": 46}, {"name": "TLBIVAAE1", "msb": 45, "lsb": 45}, {"name": "TLBIASIDE1", "msb": 44, "lsb": 44}, {"name": "TLBIVAE1", "msb": 43, "lsb": 43}, {"name": "TLBIVMALLE1", "msb": 42, "lsb": 42}, {"name": "TLBIRVAALE1", "msb": 41, "lsb": 41}, {"name": "TLBIRVALE1", "msb": 40, "lsb": 40}, {"name": "TLBIRVAAE1", "msb": 39, "lsb": 39}, {"name": "TLBIRVAE1", "msb": 38, "lsb": 38}, {"name": "TLBIRVAALE1IS", "msb": 37, "lsb": 37}, {"name": "TLBIRVALE1IS", "msb": 36, "lsb": 36}, {"name": "TLBIRVAAE1IS", "msb": 35, "lsb": 35}, {"name": "TLBIRVAE1IS", "msb": 34, "lsb": 34}, {"name": "TLBIVAALE1IS", "msb": 33, "lsb": 33}, {"name": "TLBIVALE1IS", "msb": 32, "lsb": 32}, {"name": "TLBIVAAE1IS", "msb": 31, "lsb": 31}, {"name": "TLBIASIDE1IS", "msb": 30, "lsb": 30}, {"name": "TLBIVAE1IS", "msb": 29, "lsb": 29}, {"name": "TLBIVMALLE1IS", "msb": 28, "lsb": 28}, {"name": "TLBIRVAALE1OS", "msb": 27, "lsb": 27}, {"name": "TLBIRVALE1OS", "msb": 26, "lsb": 26}, {"name": "TLBIRVAAE1OS", "msb": 25, "lsb": 25}, {"name": "TLBIRVAE1OS", "msb": 24, "lsb": 24}, {"name": "TLBIVAALE1OS", "msb": 23, "lsb": 23}, {"name": "TLBIVALE1OS", "msb": 22, "lsb": 22}, {"name": "TLBIVAAE1OS", "msb": 21, "lsb": 21}, {"name": "TLBIASIDE1OS", "msb": 20, "lsb": 20}, {"name": "TLBIVAE1OS", "msb": 19, "lsb": 19}, {"name": "TLBIVMALLE1OS", "msb": 18, "lsb": 18}, {"name": "ATS1E1WP", "msb": 17, "lsb": 17}, {"name": "ATS1E1RP", "msb": 16, "lsb": 16}, {"name": "ATS1E0W", "msb": 15, "lsb": 15}, {"name": "ATS1E0R", "msb": 14, "lsb": 14}, {"name": "ATS1E1W", "msb": 13, "lsb": 13}, {"name": "ATS1E1R", "msb": 12, "lsb": 12}, {"name": "DCZVA", "msb": 11, "lsb": 11}, {"name": "DCCIVAC", "msb": 10, "lsb": 10}, {"name": "DCCVADP", "msb": 9, "lsb": 9}, {"name": "DCCVAP", "msb": 8, "lsb": 8}, {"name": "DCCVAU", "msb": 7, "lsb": 7}, {"name": "DCCISW", "msb": 6, "lsb": 6}, {"name": "DCCSW", "msb": 5, "lsb": 5}, {"name": "DCISW", "msb": 4, "lsb": 4}, {"name": "DCIVAC", "msb": 3, "lsb": 3}, {"name": "ICIVAU", "msb": 2, "lsb": 2}, {"name": "ICIALLU", "msb": 1, "lsb": 1}, {"name": "ICIALLUIS", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "HFGRTR_EL2", "fullname": "Hypervisor Fine-Grained Read Trap Register", "enc": [3, 4, 1, 1, 4], "fieldsets": [{"instance": "HFGRTR_EL2", "fields": [{"name": "nACCDATA_EL1", "msb": 50, "lsb": 50}, {"name": "ERXADDR_EL1", "msb": 49, "lsb": 49}, {"name": "ERXPFGCDN_EL1", "msb": 48, "lsb": 48}, {"name": "ERXPFGCTL_EL1", "msb": 47, "lsb": 47}, {"name": "ERXPFGF_EL1", "msb": 46, "lsb": 46}, {"name": "ERXMISCn_EL1", "msb": 45, "lsb": 45}, {"name": "ERXSTATUS_EL1", "msb": 44, "lsb": 44}, {"name": "ERXCTLR_EL1", "msb": 43, "lsb": 43}, {"name": "ERXFR_EL1", "msb": 42, "lsb": 42}, {"name": "ERRSELR_EL1", "msb": 41, "lsb": 41}, {"name": "ERRIDR_EL1", "msb": 40, "lsb": 40}, {"name": "ICC_IGRPENn_EL1", "msb": 39, "lsb": 39}, {"name": "VBAR_EL1", "msb": 38, "lsb": 38}, {"name": "TTBR1_EL1", "msb": 37, "lsb": 37}, {"name": "TTBR0_EL1", "msb": 36, "lsb": 36}, {"name": "TPIDR_EL0", "msb": 35, "lsb": 35}, {"name": "TPIDRRO_EL0", "msb": 34, "lsb": 34}, {"name": "TPIDR_EL1", "msb": 33, "lsb": 33}, {"name": "TCR_EL1", "msb": 32, "lsb": 32}, {"name": "SCXTNUM_EL0", "msb": 31, "lsb": 31}, {"name": "SCXTNUM_EL1", "msb": 30, "lsb": 30}, {"name": "SCTLR_EL1", "msb": 29, "lsb": 29}, {"name": "REVIDR_EL1", "msb": 28, "lsb": 28}, {"name": "PAR_EL1", "msb": 27, "lsb": 27}, {"name": "MPIDR_EL1", "msb": 26, "lsb": 26}, {"name": "MIDR_EL1", "msb": 25, "lsb": 25}, {"name": "MAIR_EL1", "msb": 24, "lsb": 24}, {"name": "LORSA_EL1", "msb": 23, "lsb": 23}, {"name": "LORN_EL1", "msb": 22, "lsb": 22}, {"name": "LORID_EL1", "msb": 21, "lsb": 21}, {"name": "LOREA_EL1", "msb": 20, "lsb": 20}, {"name": "LORC_EL1", "msb": 19, "lsb": 19}, {"name": "ISR_EL1", "msb": 18, "lsb": 18}, {"name": "FAR_EL1", "msb": 17, "lsb": 17}, {"name": "ESR_EL1", "msb": 16, "lsb": 16}, {"name": "DCZID_EL0", "msb": 15, "lsb": 15}, {"name": "CTR_EL0", "msb": 14, "lsb": 14}, {"name": "CSSELR_EL1", "msb": 13, "lsb": 13}, {"name": "CPACR_EL1", "msb": 12, "lsb": 12}, {"name": "CONTEXTIDR_EL1", "msb": 11, "lsb": 11}, {"name": "CLIDR_EL1", "msb": 10, "lsb": 10}, {"name": "CCSIDR_EL1", "msb": 9, "lsb": 9}, {"name": "APIBKey", "msb": 8, "lsb": 8}, {"name": "APIAKey", "msb": 7, "lsb": 7}, {"name": "APGAKey", "msb": 6, "lsb": 6}, {"name": "APDBKey", "msb": 5, "lsb": 5}, {"name": "APDAKey", "msb": 4, "lsb": 4}, {"name": "AMAIR_EL1", "msb": 3, "lsb": 3}, {"name": "AIDR_EL1", "msb": 2, "lsb": 2}, {"name": "AFSR1_EL1", "msb": 1, "lsb": 1}, {"name": "AFSR0_EL1", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "HFGWTR_EL2", "fullname": "Hypervisor Fine-Grained Write Trap Register", "enc": [3, 4, 1, 1, 5], "fieldsets": [{"instance": "HFGWTR_EL2", "fields": [{"name": "nACCDATA_EL1", "msb": 50, "lsb": 50}, {"name": "ERXADDR_EL1", "msb": 49, "lsb": 49}, {"name": "ERXPFGCDN_EL1", "msb": 48, "lsb": 48}, {"name": "ERXPFGCTL_EL1", "msb": 47, "lsb": 47}, {"name": "ERXMISCn_EL1", "msb": 45, "lsb": 45}, {"name": "ERXSTATUS_EL1", "msb": 44, "lsb": 44}, {"name": "ERXCTLR_EL1", "msb": 43, "lsb": 43}, {"name": "ERRSELR_EL1", "msb": 41, "lsb": 41}, {"name": "ICC_IGRPENn_EL1", "msb": 39, "lsb": 39}, {"name": "VBAR_EL1", "msb": 38, "lsb": 38}, {"name": "TTBR1_EL1", "msb": 37, "lsb": 37}, {"name": "TTBR0_EL1", "msb": 36, "lsb": 36}, {"name": "TPIDR_EL0", "msb": 35, "lsb": 35}, {"name": "TPIDRRO_EL0", "msb": 34, "lsb": 34}, {"name": "TPIDR_EL1", "msb": 33, "lsb": 33}, {"name": "TCR_EL1", "msb": 32, "lsb": 32}, {"name": "SCXTNUM_EL0", "msb": 31, "lsb": 31}, {"name": "SCXTNUM_EL1", "msb": 30, "lsb": 30}, {"name": "SCTLR_EL1", "msb": 29, "lsb": 29}, {"name": "PAR_EL1", "msb": 27, "lsb": 27}, {"name": "MAIR_EL1", "msb": 24, "lsb": 24}, {"name": "LORSA_EL1", "msb": 23, "lsb": 23}, {"name": "LORN_EL1", "msb": 22, "lsb": 22}, {"name": "LOREA_EL1", "msb": 20, "lsb": 20}, {"name": "LORC_EL1", "msb": 19, "lsb": 19}, {"name": "FAR_EL1", "msb": 17, "lsb": 17}, {"name": "ESR_EL1", "msb": 16, "lsb": 16}, {"name": "CSSELR_EL1", "msb": 13, "lsb": 13}, {"name": "CPACR_EL1", "msb": 12, "lsb": 12}, {"name": "CONTEXTIDR_EL1", "msb": 11, "lsb": 11}, {"name": "APIBKey", "msb": 8, "lsb": 8}, {"name": "APIAKey", "msb": 7, "lsb": 7}, {"name": "APGAKey", "msb": 6, "lsb": 6}, {"name": "APDBKey", "msb": 5, "lsb": 5}, {"name": "APDAKey", "msb": 4, "lsb": 4}, {"name": "AMAIR_EL1", "msb": 3, "lsb": 3}, {"name": "AFSR1_EL1", "msb": 1, "lsb": 1}, {"name": "AFSR0_EL1", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "HPFAR_EL2", "fullname": "Hypervisor IPA Fault Address Register", "enc": [3, 4, 6, 0, 4], "fieldsets": [{"fields": [{"name": "NS", "msb": 63, "lsb": 63}, {"name": "FIPA", "msb": 43, "lsb": 4}]}], "width": 64}, {"index": 0, "name": "HSTR_EL2", "fullname": "Hypervisor System Trap Register", "enc": [3, 4, 1, 1, 3], "fieldsets": [{"fields": [{"name": "T<n>", "msb": 15, "lsb": 15}, {"name": "T15", "msb": 15, "lsb": 15}, {"name": "T13", "msb": 13, "lsb": 13}, {"name": "T12", "msb": 12, "lsb": 12}, {"name": "T11", "msb": 11, "lsb": 11}, {"name": "T10", "msb": 10, "lsb": 10}, {"name": "T9", "msb": 9, "lsb": 9}, {"name": "T8", "msb": 8, "lsb": 8}, {"name": "T7", "msb": 7, "lsb": 7}, {"name": "T6", "msb": 6, "lsb": 6}, {"name": "T5", "msb": 5, "lsb": 5}, {"name": "T3", "msb": 3, "lsb": 3}, {"name": "T2", "msb": 2, "lsb": 2}, {"name": "T1", "msb": 1, "lsb": 1}, {"name": "T0", "msb": 0, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ICC_AP0R0_EL1", "fullname": "Interrupt Controller Active Priorities Group 0 Registers", "enc": [3, 0, 12, 8, 4], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 1, "name": "ICC_AP0R1_EL1", "fullname": "Interrupt Controller Active Priorities Group 0 Registers", "enc": [3, 0, 12, 8, 4], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 2, "name": "ICC_AP0R2_EL1", "fullname": "Interrupt Controller Active Priorities Group 0 Registers", "enc": [3, 0, 12, 8, 4], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 3, "name": "ICC_AP0R3_EL1", "fullname": "Interrupt Controller Active Priorities Group 0 Registers", "enc": [3, 0, 12, 8, 4], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_AP1R0_EL1", "fullname": "Interrupt Controller Active Priorities Group 1 Registers", "enc": [3, 0, 12, 9, 0], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 1, "name": "ICC_AP1R1_EL1", "fullname": "Interrupt Controller Active Priorities Group 1 Registers", "enc": [3, 0, 12, 9, 0], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 2, "name": "ICC_AP1R2_EL1", "fullname": "Interrupt Controller Active Priorities Group 1 Registers", "enc": [3, 0, 12, 9, 0], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 3, "name": "ICC_AP1R3_EL1", "fullname": "Interrupt Controller Active Priorities Group 1 Registers", "enc": [3, 0, 12, 9, 0], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_ASGI1R_EL1", "fullname": "Interrupt Controller Alias Software Generated Interrupt Group 1 Register", "enc": [3, 0, 12, 11, 6], "fieldsets": [{"fields": [{"name": "Aff3", "msb": 55, "lsb": 48}, {"name": "RS", "msb": 47, "lsb": 44}, {"name": "IRM", "msb": 40, "lsb": 40}, {"name": "Aff2", "msb": 39, "lsb": 32}, {"name": "INTID", "msb": 27, "lsb": 24}, {"name": "Aff1", "msb": 23, "lsb": 16}, {"name": "TargetList", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_BPR0_EL1", "fullname": "Interrupt Controller Binary Point Register 0", "enc": [3, 0, 12, 8, 3], "fieldsets": [{"fields": [{"name": "BinaryPoint", "msb": 2, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_BPR1_EL1", "fullname": "Interrupt Controller Binary Point Register 1", "enc": [3, 0, 12, 12, 3], "fieldsets": [{"fields": [{"name": "BinaryPoint", "msb": 2, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_CTLR_EL1", "fullname": "Interrupt Controller Control Register (EL1)", "enc": [3, 0, 12, 12, 4], "fieldsets": [{"fields": [{"name": "ExtRange", "msb": 19, "lsb": 19}, {"name": "RSS", "msb": 18, "lsb": 18}, {"name": "A3V", "msb": 15, "lsb": 15}, {"name": "SEIS", "msb": 14, "lsb": 14}, {"name": "IDbits", "msb": 13, "lsb": 11}, {"name": "PRIbits", "msb": 10, "lsb": 8}, {"name": "PMHE", "msb": 6, "lsb": 6}, {"name": "EOImode", "msb": 1, "lsb": 1}, {"name": "CBPR", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_CTLR_EL3", "fullname": "Interrupt Controller Control Register (EL3)", "enc": [3, 6, 12, 12, 4], "fieldsets": [{"fields": [{"name": "ExtRange", "msb": 19, "lsb": 19}, {"name": "RSS", "msb": 18, "lsb": 18}, {"name": "nDS", "msb": 17, "lsb": 17}, {"name": "A3V", "msb": 15, "lsb": 15}, {"name": "SEIS", "msb": 14, "lsb": 14}, {"name": "IDbits", "msb": 13, "lsb": 11}, {"name": "PRIbits", "msb": 10, "lsb": 8}, {"name": "PMHE", "msb": 6, "lsb": 6}, {"name": "RM", "msb": 5, "lsb": 5}, {"name": "EOImode_EL1NS", "msb": 4, "lsb": 4}, {"name": "EOImode_EL1S", "msb": 3, "lsb": 3}, {"name": "EOImode_EL3", "msb": 2, "lsb": 2}, {"name": "CBPR_EL1NS", "msb": 1, "lsb": 1}, {"name": "CBPR_EL1S", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_DIR_EL1", "fullname": "Interrupt Controller Deactivate Interrupt Register", "enc": [3, 0, 12, 11, 1], "fieldsets": [{"fields": [{"name": "INTID", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_EOIR0_EL1", "fullname": "Interrupt Controller End Of Interrupt Register 0", "enc": [3, 0, 12, 8, 1], "fieldsets": [{"fields": [{"name": "INTID", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_EOIR1_EL1", "fullname": "Interrupt Controller End Of Interrupt Register 1", "enc": [3, 0, 12, 12, 1], "fieldsets": [{"fields": [{"name": "INTID", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_HPPIR0_EL1", "fullname": "Interrupt Controller Highest Priority Pending Interrupt Register 0", "enc": [3, 0, 12, 8, 2], "fieldsets": [{"fields": [{"name": "INTID", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_HPPIR1_EL1", "fullname": "Interrupt Controller Highest Priority Pending Interrupt Register 1", "enc": [3, 0, 12, 12, 2], "fieldsets": [{"fields": [{"name": "INTID", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_IAR0_EL1", "fullname": "Interrupt Controller Interrupt Acknowledge Register 0", "enc": [3, 0, 12, 8, 0], "fieldsets": [{"fields": [{"name": "INTID", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_IAR1_EL1", "fullname": "Interrupt Controller Interrupt Acknowledge Register 1", "enc": [3, 0, 12, 12, 0], "fieldsets": [{"fields": [{"name": "INTID", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_IGRPEN0_EL1", "fullname": "Interrupt Controller Interrupt Group 0 Enable register", "enc": [3, 0, 12, 12, 6], "fieldsets": [{"fields": [{"name": "Enable", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_IGRPEN1_EL1", "fullname": "Interrupt Controller Interrupt Group 1 Enable register", "enc": [3, 0, 12, 12, 7], "fieldsets": [{"fields": [{"name": "Enable", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_IGRPEN1_EL3", "fullname": "Interrupt Controller Interrupt Group 1 Enable register (EL3)", "enc": [3, 6, 12, 12, 7], "fieldsets": [{"fields": [{"name": "EnableGrp1S", "msb": 1, "lsb": 1}, {"name": "EnableGrp1NS", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_PMR_EL1", "fullname": "Interrupt Controller Interrupt Priority Mask Register", "enc": [3, 0, 4, 6, 0], "fieldsets": [{"fields": [{"name": "Priority", "msb": 7, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_RPR_EL1", "fullname": "Interrupt Controller Running Priority Register", "enc": [3, 0, 12, 11, 3], "fieldsets": [{"fields": [{"name": "Priority", "msb": 7, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_SGI0R_EL1", "fullname": "Interrupt Controller Software Generated Interrupt Group 0 Register", "enc": [3, 0, 12, 11, 7], "fieldsets": [{"fields": [{"name": "Aff3", "msb": 55, "lsb": 48}, {"name": "RS", "msb": 47, "lsb": 44}, {"name": "IRM", "msb": 40, "lsb": 40}, {"name": "Aff2", "msb": 39, "lsb": 32}, {"name": "INTID", "msb": 27, "lsb": 24}, {"name": "Aff1", "msb": 23, "lsb": 16}, {"name": "TargetList", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_SGI1R_EL1", "fullname": "Interrupt Controller Software Generated Interrupt Group 1 Register", "enc": [3, 0, 12, 11, 5], "fieldsets": [{"fields": [{"name": "Aff3", "msb": 55, "lsb": 48}, {"name": "RS", "msb": 47, "lsb": 44}, {"name": "IRM", "msb": 40, "lsb": 40}, {"name": "Aff2", "msb": 39, "lsb": 32}, {"name": "INTID", "msb": 27, "lsb": 24}, {"name": "Aff1", "msb": 23, "lsb": 16}, {"name": "TargetList", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_SRE_EL1", "fullname": "Interrupt Controller System Register Enable register (EL1)", "enc": [3, 0, 12, 12, 5], "fieldsets": [{"fields": [{"name": "DIB", "msb": 2, "lsb": 2}, {"name": "DFB", "msb": 1, "lsb": 1}, {"name": "SRE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_SRE_EL2", "fullname": "Interrupt Controller System Register Enable register (EL2)", "enc": [3, 4, 12, 9, 5], "fieldsets": [{"fields": [{"name": "Enable", "msb": 3, "lsb": 3}, {"name": "DIB", "msb": 2, "lsb": 2}, {"name": "DFB", "msb": 1, "lsb": 1}, {"name": "SRE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_SRE_EL3", "fullname": "Interrupt Controller System Register Enable register (EL3)", "enc": [3, 6, 12, 12, 5], "fieldsets": [{"fields": [{"name": "Enable", "msb": 3, "lsb": 3}, {"name": "DIB", "msb": 2, "lsb": 2}, {"name": "DFB", "msb": 1, "lsb": 1}, {"name": "SRE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICH_AP0R0_EL2", "fullname": "Interrupt Controller Hyp Active Priorities Group 0 Registers", "enc": [3, 4, 12, 8, 0], "fieldsets": [{"fields": [{"name": "P<x>", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 1, "name": "ICH_AP0R1_EL2", "fullname": "Interrupt Controller Hyp Active Priorities Group 0 Registers", "enc": [3, 4, 12, 8, 0], "fieldsets": [{"fields": [{"name": "P<x>", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 2, "name": "ICH_AP0R2_EL2", "fullname": "Interrupt Controller Hyp Active Priorities Group 0 Registers", "enc": [3, 4, 12, 8, 0], "fieldsets": [{"fields": [{"name": "P<x>", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 3, "name": "ICH_AP0R3_EL2", "fullname": "Interrupt Controller Hyp Active Priorities Group 0 Registers", "enc": [3, 4, 12, 8, 0], "fieldsets": [{"fields": [{"name": "P<x>", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICH_AP1R0_EL2", "fullname": "Interrupt Controller Hyp Active Priorities Group 1 Registers", "enc": [3, 4, 12, 9, 0], "fieldsets": [{"fields": [{"name": "P<x>", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 1, "name": "ICH_AP1R1_EL2", "fullname": "Interrupt Controller Hyp Active Priorities Group 1 Registers", "enc": [3, 4, 12, 9, 0], "fieldsets": [{"fields": [{"name": "P<x>", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 2, "name": "ICH_AP1R2_EL2", "fullname": "Interrupt Controller Hyp Active Priorities Group 1 Registers", "enc": [3, 4, 12, 9, 0], "fieldsets": [{"fields": [{"name": "P<x>", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 3, "name": "ICH_AP1R3_EL2", "fullname": "Interrupt Controller Hyp Active Priorities Group 1 Registers", "enc": [3, 4, 12, 9, 0], "fieldsets": [{"fields": [{"name": "P<x>", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICH_EISR_EL2", "fullname": "Interrupt Controller End of Interrupt Status Register", "enc": [3, 4, 12, 11, 3], "fieldsets": [{"fields": [{"name": "Status<n>", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICH_ELRSR_EL2", "fullname": "Interrupt Controller Empty List Register Status Register", "enc": [3, 4, 12, 11, 5], "fieldsets": [{"fields": [{"name": "Status<n>", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICH_HCR_EL2", "fullname": "Interrupt Controller Hyp Control Register", "enc": [3, 4, 12, 11, 0], "fieldsets": [{"fields": [{"name": "EOIcount", "msb": 31, "lsb": 27}, {"name": "DVIM", "msb": 15, "lsb": 15}, {"name": "TDIR", "msb": 14, "lsb": 14}, {"name": "TSEI", "msb": 13, "lsb": 13}, {"name": "TALL1", "msb": 12, "lsb": 12}, {"name": "TALL0", "msb": 11, "lsb": 11}, {"name": "TC", "msb": 10, "lsb": 10}, {"name": "vSGIEOICount", "msb": 8, "lsb": 8}, {"name": "VGrp1DIE", "msb": 7, "lsb": 7}, {"name": "VGrp1EIE", "msb": 6, "lsb": 6}, {"name": "VGrp0DIE", "msb": 5, "lsb": 5}, {"name": "VGrp0EIE", "msb": 4, "lsb": 4}, {"name": "NPIE", "msb": 3, "lsb": 3}, {"name": "LRENPIE", "msb": 2, "lsb": 2}, {"name": "UIE", "msb": 1, "lsb": 1}, {"name": "En", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICH_LR0_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 1, "name": "ICH_LR1_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 2, "name": "ICH_LR2_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 3, "name": "ICH_LR3_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 4, "name": "ICH_LR4_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 5, "name": "ICH_LR5_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 6, "name": "ICH_LR6_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 7, "name": "ICH_LR7_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 8, "name": "ICH_LR8_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 9, "name": "ICH_LR9_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 10, "name": "ICH_LR10_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 11, "name": "ICH_LR11_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 12, "name": "ICH_LR12_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 13, "name": "ICH_LR13_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 14, "name": "ICH_LR14_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 15, "name": "ICH_LR15_EL2", "fullname": "Interrupt Controller List Registers", "enc": [3, 4, 12, 12, 0], "fieldsets": [{"fields": [{"name": "State", "msb": 63, "lsb": 62}, {"name": "HW", "msb": 61, "lsb": 61}, {"name": "Group", "msb": 60, "lsb": 60}, {"name": "Priority", "msb": 55, "lsb": 48}, {"name": "pINTID", "msb": 44, "lsb": 32}, {"name": "vINTID", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICH_MISR_EL2", "fullname": "Interrupt Controller Maintenance Interrupt State Register", "enc": [3, 4, 12, 11, 2], "fieldsets": [{"fields": [{"name": "VGrp1D", "msb": 7, "lsb": 7}, {"name": "VGrp1E", "msb": 6, "lsb": 6}, {"name": "VGrp0D", "msb": 5, "lsb": 5}, {"name": "VGrp0E", "msb": 4, "lsb": 4}, {"name": "NP", "msb": 3, "lsb": 3}, {"name": "LRENP", "msb": 2, "lsb": 2}, {"name": "U", "msb": 1, "lsb": 1}, {"name": "EOI", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICH_VMCR_EL2", "fullname": "Interrupt Controller Virtual Machine Control Register", "enc": [3, 4, 12, 11, 7], "fieldsets": [{"fields": [{"name": "VPMR", "msb": 31, "lsb": 24}, {"name": "VBPR0", "msb": 23, "lsb": 21}, {"name": "VBPR1", "msb": 20, "lsb": 18}, {"name": "VEOIM", "msb": 9, "lsb": 9}, {"name": "VCBPR", "msb": 4, "lsb": 4}, {"name": "VFIQEn", "msb": 3, "lsb": 3}, {"name": "VAckCtl", "msb": 2, "lsb": 2}, {"name": "VENG1", "msb": 1, "lsb": 1}, {"name": "VENG0", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICH_VTR_EL2", "fullname": "Interrupt Controller VGIC Type Register", "enc": [3, 4, 12, 11, 1], "fieldsets": [{"fields": [{"name": "PRIbits", "msb": 31, "lsb": 29}, {"name": "PREbits", "msb": 28, "lsb": 26}, {"name": "IDbits", "msb": 25, "lsb": 23}, {"name": "SEIS", "msb": 22, "lsb": 22}, {"name": "A3V", "msb": 21, "lsb": 21}, {"name": "nV4", "msb": 20, "lsb": 20}, {"name": "TDS", "msb": 19, "lsb": 19}, {"name": "DVIM", "msb": 18, "lsb": 18}, {"name": "ListRegs", "msb": 4, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_AP0R0_EL1", "fullname": "Interrupt Controller Virtual Active Priorities Group 0 Registers", "enc": [3, 0, 12, 8, 4], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 1, "name": "ICC_AP0R1_EL1", "fullname": "Interrupt Controller Virtual Active Priorities Group 0 Registers", "enc": [3, 0, 12, 8, 4], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 2, "name": "ICC_AP0R2_EL1", "fullname": "Interrupt Controller Virtual Active Priorities Group 0 Registers", "enc": [3, 0, 12, 8, 4], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 3, "name": "ICC_AP0R3_EL1", "fullname": "Interrupt Controller Virtual Active Priorities Group 0 Registers", "enc": [3, 0, 12, 8, 4], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_AP1R0_EL1", "fullname": "Interrupt Controller Virtual Active Priorities Group 1 Registers", "enc": [3, 0, 12, 9, 0], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 1, "name": "ICC_AP1R1_EL1", "fullname": "Interrupt Controller Virtual Active Priorities Group 1 Registers", "enc": [3, 0, 12, 9, 0], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 2, "name": "ICC_AP1R2_EL1", "fullname": "Interrupt Controller Virtual Active Priorities Group 1 Registers", "enc": [3, 0, 12, 9, 0], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 3, "name": "ICC_AP1R3_EL1", "fullname": "Interrupt Controller Virtual Active Priorities Group 1 Registers", "enc": [3, 0, 12, 9, 0], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_BPR0_EL1", "fullname": "Interrupt Controller Virtual Binary Point Register 0", "enc": [3, 0, 12, 8, 3], "fieldsets": [{"fields": [{"name": "BinaryPoint", "msb": 2, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_BPR1_EL1", "fullname": "Interrupt Controller Virtual Binary Point Register 1", "enc": [3, 0, 12, 12, 3], "fieldsets": [{"fields": [{"name": "BinaryPoint", "msb": 2, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_CTLR_EL1", "fullname": "Interrupt Controller Virtual Control Register", "enc": [3, 0, 12, 12, 4], "fieldsets": [{"fields": [{"name": "ExtRange", "msb": 19, "lsb": 19}, {"name": "RSS", "msb": 18, "lsb": 18}, {"name": "A3V", "msb": 15, "lsb": 15}, {"name": "SEIS", "msb": 14, "lsb": 14}, {"name": "IDbits", "msb": 13, "lsb": 11}, {"name": "PRIbits", "msb": 10, "lsb": 8}, {"name": "EOImode", "msb": 1, "lsb": 1}, {"name": "CBPR", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_DIR_EL1", "fullname": "Interrupt Controller Deactivate Virtual Interrupt Register", "enc": [3, 0, 12, 11, 1], "fieldsets": [{"fields": [{"name": "INTID", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_EOIR0_EL1", "fullname": "Interrupt Controller Virtual End Of Interrupt Register 0", "enc": [3, 0, 12, 8, 1], "fieldsets": [{"fields": [{"name": "INTID", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_EOIR1_EL1", "fullname": "Interrupt Controller Virtual End Of Interrupt Register 1", "enc": [3, 0, 12, 12, 1], "fieldsets": [{"fields": [{"name": "INTID", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_HPPIR0_EL1", "fullname": "Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0", "enc": [3, 0, 12, 8, 2], "fieldsets": [{"fields": [{"name": "INTID", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_HPPIR1_EL1", "fullname": "Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1", "enc": [3, 0, 12, 12, 2], "fieldsets": [{"fields": [{"name": "INTID", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_IAR0_EL1", "fullname": "Interrupt Controller Virtual Interrupt Acknowledge Register 0", "enc": [3, 0, 12, 8, 0], "fieldsets": [{"fields": [{"name": "INTID", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_IAR1_EL1", "fullname": "Interrupt Controller Virtual Interrupt Acknowledge Register 1", "enc": [3, 0, 12, 12, 0], "fieldsets": [{"fields": [{"name": "INTID", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_IGRPEN0_EL1", "fullname": "Interrupt Controller Virtual Interrupt Group 0 Enable register", "enc": [3, 0, 12, 12, 6], "fieldsets": [{"fields": [{"name": "Enable", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_IGRPEN1_EL1", "fullname": "Interrupt Controller Virtual Interrupt Group 1 Enable register", "enc": [3, 0, 12, 12, 7], "fieldsets": [{"fields": [{"name": "Enable", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_PMR_EL1", "fullname": "Interrupt Controller Virtual Interrupt Priority Mask Register", "enc": [3, 0, 4, 6, 0], "fieldsets": [{"fields": [{"name": "Priority", "msb": 7, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ICC_RPR_EL1", "fullname": "Interrupt Controller Virtual Running Priority Register", "enc": [3, 0, 12, 11, 3], "fieldsets": [{"fields": [{"name": "Priority", "msb": 7, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ID_AA64AFR0_EL1", "fullname": "AArch64 Auxiliary Feature Register 0", "enc": [3, 0, 0, 5, 4], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 31, "lsb": 28}, {"name": "IMPLEMENTATION DEFINED", "msb": 27, "lsb": 24}, {"name": "IMPLEMENTATION DEFINED", "msb": 23, "lsb": 20}, {"name": "IMPLEMENTATION DEFINED", "msb": 19, "lsb": 16}, {"name": "IMPLEMENTATION DEFINED", "msb": 15, "lsb": 12}, {"name": "IMPLEMENTATION DEFINED", "msb": 11, "lsb": 8}, {"name": "IMPLEMENTATION DEFINED", "msb": 7, "lsb": 4}, {"name": "IMPLEMENTATION DEFINED", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ID_AA64AFR1_EL1", "fullname": "AArch64 Auxiliary Feature Register 1", "enc": [3, 0, 0, 5, 5], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "ID_AA64DFR0_EL1", "fullname": "AArch64 Debug Feature Register 0", "enc": [3, 0, 0, 5, 0], "fieldsets": [{"fields": [{"name": "MTPMU", "msb": 51, "lsb": 48}, {"name": "TraceFilt", "msb": 43, "lsb": 40}, {"name": "DoubleLock", "msb": 39, "lsb": 36}, {"name": "PMSVer", "msb": 35, "lsb": 32}, {"name": "CTX_CMPs", "msb": 31, "lsb": 28}, {"name": "WRPs", "msb": 23, "lsb": 20}, {"name": "BRPs", "msb": 15, "lsb": 12}, {"name": "PMUVer", "msb": 11, "lsb": 8}, {"name": "TraceVer", "msb": 7, "lsb": 4}, {"name": "DebugVer", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ID_AA64DFR1_EL1", "fullname": "AArch64 Debug Feature Register 1", "enc": [3, 0, 0, 5, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "ID_AA64ISAR0_EL1", "fullname": "AArch64 Instruction Set Attribute Register 0", "enc": [3, 0, 0, 6, 0], "fieldsets": [{"fields": [{"name": "RNDR", "msb": 63, "lsb": 60}, {"name": "TLB", "msb": 59, "lsb": 56}, {"name": "TS", "msb": 55, "lsb": 52}, {"name": "FHM", "msb": 51, "lsb": 48}, {"name": "DP", "msb": 47, "lsb": 44}, {"name": "SM4", "msb": 43, "lsb": 40}, {"name": "SM3", "msb": 39, "lsb": 36}, {"name": "SHA3", "msb": 35, "lsb": 32}, {"name": "RDM", "msb": 31, "lsb": 28}, {"name": "Atomic", "msb": 23, "lsb": 20}, {"name": "CRC32", "msb": 19, "lsb": 16}, {"name": "SHA2", "msb": 15, "lsb": 12}, {"name": "SHA1", "msb": 11, "lsb": 8}, {"name": "AES", "msb": 7, "lsb": 4}]}], "width": 64}, {"index": 0, "name": "ID_AA64ISAR1_EL1", "fullname": "AArch64 Instruction Set Attribute Register 1", "enc": [3, 0, 0, 6, 1], "fieldsets": [{"fields": [{"name": "LS64", "msb": 63, "lsb": 60}, {"name": "XS", "msb": 59, "lsb": 56}, {"name": "I8MM", "msb": 55, "lsb": 52}, {"name": "DGH", "msb": 51, "lsb": 48}, {"name": "BF16", "msb": 47, "lsb": 44}, {"name": "SPECRES", "msb": 43, "lsb": 40}, {"name": "SB", "msb": 39, "lsb": 36}, {"name": "FRINTTS", "msb": 35, "lsb": 32}, {"name": "GPI", "msb": 31, "lsb": 28}, {"name": "GPA", "msb": 27, "lsb": 24}, {"name": "LRCPC", "msb": 23, "lsb": 20}, {"name": "FCMA", "msb": 19, "lsb": 16}, {"name": "JSCVT", "msb": 15, "lsb": 12}, {"name": "API", "msb": 11, "lsb": 8}, {"name": "APA", "msb": 7, "lsb": 4}, {"name": "DPB", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ID_AA64ISAR2_EL1", "fullname": "AArch64 Instruction Set Attribute Register 2", "enc": [3, 0, 0, 6, 2], "fieldsets": [{"fields": [{"name": "RPRES", "msb": 7, "lsb": 4}, {"name": "WFxT", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ID_AA64MMFR0_EL1", "fullname": "AArch64 Memory Model Feature Register 0", "enc": [3, 0, 0, 7, 0], "fieldsets": [{"fields": [{"name": "ECV", "msb": 63, "lsb": 60}, {"name": "FGT", "msb": 59, "lsb": 56}, {"name": "ExS", "msb": 47, "lsb": 44}, {"name": "TGran4_2", "msb": 43, "lsb": 40}, {"name": "TGran64_2", "msb": 39, "lsb": 36}, {"name": "TGran16_2", "msb": 35, "lsb": 32}, {"name": "TGran4", "msb": 31, "lsb": 28}, {"name": "TGran64", "msb": 27, "lsb": 24}, {"name": "TGran16", "msb": 23, "lsb": 20}, {"name": "BigEndEL0", "msb": 19, "lsb": 16}, {"name": "SNSMem", "msb": 15, "lsb": 12}, {"name": "BigEnd", "msb": 11, "lsb": 8}, {"name": "ASIDBits", "msb": 7, "lsb": 4}, {"name": "PARange", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ID_AA64MMFR1_EL1", "fullname": "AArch64 Memory Model Feature Register 1", "enc": [3, 0, 0, 7, 1], "fieldsets": [{"fields": [{"name": "nTLBPA", "msb": 51, "lsb": 48}, {"name": "AFP", "msb": 47, "lsb": 44}, {"name": "HCX", "msb": 43, "lsb": 40}, {"name": "ETS", "msb": 39, "lsb": 36}, {"name": "TWED", "msb": 35, "lsb": 32}, {"name": "XNX", "msb": 31, "lsb": 28}, {"name": "SpecSEI", "msb": 27, "lsb": 24}, {"name": "PAN", "msb": 23, "lsb": 20}, {"name": "LO", "msb": 19, "lsb": 16}, {"name": "HPDS", "msb": 15, "lsb": 12}, {"name": "VH", "msb": 11, "lsb": 8}, {"name": "VMIDBits", "msb": 7, "lsb": 4}, {"name": "HAFDBS", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ID_AA64MMFR2_EL1", "fullname": "AArch64 Memory Model Feature Register 2", "enc": [3, 0, 0, 7, 2], "fieldsets": [{"fields": [{"name": "E0PD", "msb": 63, "lsb": 60}, {"name": "EVT", "msb": 59, "lsb": 56}, {"name": "BBM", "msb": 55, "lsb": 52}, {"name": "TTL", "msb": 51, "lsb": 48}, {"name": "FWB", "msb": 43, "lsb": 40}, {"name": "IDS", "msb": 39, "lsb": 36}, {"name": "AT", "msb": 35, "lsb": 32}, {"name": "ST", "msb": 31, "lsb": 28}, {"name": "NV", "msb": 27, "lsb": 24}, {"name": "CCIDX", "msb": 23, "lsb": 20}, {"name": "VARange", "msb": 19, "lsb": 16}, {"name": "IESB", "msb": 15, "lsb": 12}, {"name": "LSM", "msb": 11, "lsb": 8}, {"name": "UAO", "msb": 7, "lsb": 4}, {"name": "CnP", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ID_AA64PFR0_EL1", "fullname": "AArch64 Processor Feature Register 0", "enc": [3, 0, 0, 4, 0], "fieldsets": [{"fields": [{"name": "CSV3", "msb": 63, "lsb": 60}, {"name": "CSV2", "msb": 59, "lsb": 56}, {"name": "DIT", "msb": 51, "lsb": 48}, {"name": "AMU", "msb": 47, "lsb": 44}, {"name": "MPAM", "msb": 43, "lsb": 40}, {"name": "SEL2", "msb": 39, "lsb": 36}, {"name": "SVE", "msb": 35, "lsb": 32}, {"name": "RAS", "msb": 31, "lsb": 28}, {"name": "GIC", "msb": 27, "lsb": 24}, {"name": "AdvSIMD", "msb": 23, "lsb": 20}, {"name": "FP", "msb": 19, "lsb": 16}, {"name": "EL3", "msb": 15, "lsb": 12}, {"name": "EL2", "msb": 11, "lsb": 8}, {"name": "EL1", "msb": 7, "lsb": 4}, {"name": "EL0", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ID_AA64PFR1_EL1", "fullname": "AArch64 Processor Feature Register 1", "enc": [3, 0, 0, 4, 1], "fieldsets": [{"fields": [{"name": "CSV2_frac", "msb": 35, "lsb": 32}, {"name": "MPAM_frac", "msb": 19, "lsb": 16}, {"name": "RAS_frac", "msb": 15, "lsb": 12}, {"name": "MTE", "msb": 11, "lsb": 8}, {"name": "SSBS", "msb": 7, "lsb": 4}, {"name": "BT", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ID_AA64ZFR0_EL1", "fullname": "SVE Feature ID register 0", "enc": [3, 0, 0, 4, 4], "fieldsets": [{"fields": [{"name": "F64MM", "msb": 59, "lsb": 56}, {"name": "F32MM", "msb": 55, "lsb": 52}, {"name": "I8MM", "msb": 47, "lsb": 44}, {"name": "BF16", "msb": 23, "lsb": 20}, {"name": "SVEver", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ID_AFR0_EL1", "fullname": "AArch32 Auxiliary Feature Register 0", "enc": [3, 0, 0, 1, 3], "fieldsets": [{"fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 15, "lsb": 12}, {"name": "IMPLEMENTATION DEFINED", "msb": 11, "lsb": 8}, {"name": "IMPLEMENTATION DEFINED", "msb": 7, "lsb": 4}, {"name": "IMPLEMENTATION DEFINED", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_DFR0_EL1", "fullname": "AArch32 Debug Feature Register 0", "enc": [3, 0, 0, 1, 2], "fieldsets": [{"fields": [{"name": "TraceFilt", "msb": 31, "lsb": 28}, {"name": "PerfMon", "msb": 27, "lsb": 24}, {"name": "MProfDbg", "msb": 23, "lsb": 20}, {"name": "MMapTrc", "msb": 19, "lsb": 16}, {"name": "CopTrc", "msb": 15, "lsb": 12}, {"name": "MMapDbg", "msb": 11, "lsb": 8}, {"name": "CopSDbg", "msb": 7, "lsb": 4}, {"name": "CopDbg", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_DFR1_EL1", "fullname": "Debug Feature Register 1", "enc": [3, 0, 0, 3, 5], "fieldsets": [{"instance": "ID_DFR1_EL1", "fields": [{"name": "MTPMU", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_ISAR0_EL1", "fullname": "AArch32 Instruction Set Attribute Register 0", "enc": [3, 0, 0, 2, 0], "fieldsets": [{"fields": [{"name": "Divide", "msb": 27, "lsb": 24}, {"name": "Debug", "msb": 23, "lsb": 20}, {"name": "Coproc", "msb": 19, "lsb": 16}, {"name": "CmpBranch", "msb": 15, "lsb": 12}, {"name": "BitField", "msb": 11, "lsb": 8}, {"name": "BitCount", "msb": 7, "lsb": 4}, {"name": "Swap", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_ISAR1_EL1", "fullname": "AArch32 Instruction Set Attribute Register 1", "enc": [3, 0, 0, 2, 1], "fieldsets": [{"fields": [{"name": "Jazelle", "msb": 31, "lsb": 28}, {"name": "Interwork", "msb": 27, "lsb": 24}, {"name": "Immediate", "msb": 23, "lsb": 20}, {"name": "IfThen", "msb": 19, "lsb": 16}, {"name": "Extend", "msb": 15, "lsb": 12}, {"name": "Except_AR", "msb": 11, "lsb": 8}, {"name": "Except", "msb": 7, "lsb": 4}, {"name": "Endian", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_ISAR2_EL1", "fullname": "AArch32 Instruction Set Attribute Register 2", "enc": [3, 0, 0, 2, 2], "fieldsets": [{"fields": [{"name": "Reversal", "msb": 31, "lsb": 28}, {"name": "PSR_AR", "msb": 27, "lsb": 24}, {"name": "MultU", "msb": 23, "lsb": 20}, {"name": "MultS", "msb": 19, "lsb": 16}, {"name": "Mult", "msb": 15, "lsb": 12}, {"name": "MultiAccessInt", "msb": 11, "lsb": 8}, {"name": "MemHint", "msb": 7, "lsb": 4}, {"name": "LoadStore", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_ISAR3_EL1", "fullname": "AArch32 Instruction Set Attribute Register 3", "enc": [3, 0, 0, 2, 3], "fieldsets": [{"fields": [{"name": "T32EE", "msb": 31, "lsb": 28}, {"name": "TrueNOP", "msb": 27, "lsb": 24}, {"name": "T32Copy", "msb": 23, "lsb": 20}, {"name": "TabBranch", "msb": 19, "lsb": 16}, {"name": "SynchPrim", "msb": 15, "lsb": 12}, {"name": "SVC", "msb": 11, "lsb": 8}, {"name": "SIMD", "msb": 7, "lsb": 4}, {"name": "Saturate", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_ISAR4_EL1", "fullname": "AArch32 Instruction Set Attribute Register 4", "enc": [3, 0, 0, 2, 4], "fieldsets": [{"fields": [{"name": "SWP_frac", "msb": 31, "lsb": 28}, {"name": "PSR_M", "msb": 27, "lsb": 24}, {"name": "SynchPrim_frac", "msb": 23, "lsb": 20}, {"name": "Barrier", "msb": 19, "lsb": 16}, {"name": "SMC", "msb": 15, "lsb": 12}, {"name": "Writeback", "msb": 11, "lsb": 8}, {"name": "WithShifts", "msb": 7, "lsb": 4}, {"name": "Unpriv", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_ISAR5_EL1", "fullname": "AArch32 Instruction Set Attribute Register 5", "enc": [3, 0, 0, 2, 5], "fieldsets": [{"fields": [{"name": "VCMA", "msb": 31, "lsb": 28}, {"name": "RDM", "msb": 27, "lsb": 24}, {"name": "CRC32", "msb": 19, "lsb": 16}, {"name": "SHA2", "msb": 15, "lsb": 12}, {"name": "SHA1", "msb": 11, "lsb": 8}, {"name": "AES", "msb": 7, "lsb": 4}, {"name": "SEVL", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_ISAR6_EL1", "fullname": "AArch32 Instruction Set Attribute Register 6", "enc": [3, 0, 0, 2, 7], "fieldsets": [{"fields": [{"name": "I8MM", "msb": 27, "lsb": 24}, {"name": "BF16", "msb": 23, "lsb": 20}, {"name": "SPECRES", "msb": 19, "lsb": 16}, {"name": "SB", "msb": 15, "lsb": 12}, {"name": "FHM", "msb": 11, "lsb": 8}, {"name": "DP", "msb": 7, "lsb": 4}, {"name": "JSCVT", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_MMFR0_EL1", "fullname": "AArch32 Memory Model Feature Register 0", "enc": [3, 0, 0, 1, 4], "fieldsets": [{"fields": [{"name": "InnerShr", "msb": 31, "lsb": 28}, {"name": "FCSE", "msb": 27, "lsb": 24}, {"name": "AuxReg", "msb": 23, "lsb": 20}, {"name": "TCM", "msb": 19, "lsb": 16}, {"name": "ShareLvl", "msb": 15, "lsb": 12}, {"name": "OuterShr", "msb": 11, "lsb": 8}, {"name": "PMSA", "msb": 7, "lsb": 4}, {"name": "VMSA", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_MMFR1_EL1", "fullname": "AArch32 Memory Model Feature Register 1", "enc": [3, 0, 0, 1, 5], "fieldsets": [{"fields": [{"name": "BPred", "msb": 31, "lsb": 28}, {"name": "L1TstCln", "msb": 27, "lsb": 24}, {"name": "L1Uni", "msb": 23, "lsb": 20}, {"name": "L1Hvd", "msb": 19, "lsb": 16}, {"name": "L1UniSW", "msb": 15, "lsb": 12}, {"name": "L1HvdSW", "msb": 11, "lsb": 8}, {"name": "L1UniVA", "msb": 7, "lsb": 4}, {"name": "L1HvdVA", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_MMFR2_EL1", "fullname": "AArch32 Memory Model Feature Register 2", "enc": [3, 0, 0, 1, 6], "fieldsets": [{"fields": [{"name": "HWAccFlg", "msb": 31, "lsb": 28}, {"name": "WFIStall", "msb": 27, "lsb": 24}, {"name": "MemBarr", "msb": 23, "lsb": 20}, {"name": "UniTLB", "msb": 19, "lsb": 16}, {"name": "HvdTLB", "msb": 15, "lsb": 12}, {"name": "L1HvdRng", "msb": 11, "lsb": 8}, {"name": "L1HvdBG", "msb": 7, "lsb": 4}, {"name": "L1HvdFG", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_MMFR3_EL1", "fullname": "AArch32 Memory Model Feature Register 3", "enc": [3, 0, 0, 1, 7], "fieldsets": [{"fields": [{"name": "Supersec", "msb": 31, "lsb": 28}, {"name": "CMemSz", "msb": 27, "lsb": 24}, {"name": "CohWalk", "msb": 23, "lsb": 20}, {"name": "PAN", "msb": 19, "lsb": 16}, {"name": "MaintBcst", "msb": 15, "lsb": 12}, {"name": "BPMaint", "msb": 11, "lsb": 8}, {"name": "CMaintSW", "msb": 7, "lsb": 4}, {"name": "CMaintVA", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_MMFR4_EL1", "fullname": "AArch32 Memory Model Feature Register 4", "enc": [3, 0, 0, 2, 6], "fieldsets": [{"fields": [{"name": "EVT", "msb": 31, "lsb": 28}, {"name": "CCIDX", "msb": 27, "lsb": 24}, {"name": "LSM", "msb": 23, "lsb": 20}, {"name": "HPDS", "msb": 19, "lsb": 16}, {"name": "CnP", "msb": 15, "lsb": 12}, {"name": "XNX", "msb": 11, "lsb": 8}, {"name": "AC2", "msb": 7, "lsb": 4}, {"name": "SpecSEI", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_MMFR5_EL1", "fullname": "AArch32 Memory Model Feature Register 5", "enc": [3, 0, 0, 3, 6], "fieldsets": [{"fields": [{"name": "nTLBPA", "msb": 7, "lsb": 4}, {"name": "ETS", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_PFR0_EL1", "fullname": "AArch32 Processor Feature Register 0", "enc": [3, 0, 0, 1, 0], "fieldsets": [{"fields": [{"name": "RAS", "msb": 31, "lsb": 28}, {"name": "DIT", "msb": 27, "lsb": 24}, {"name": "AMU", "msb": 23, "lsb": 20}, {"name": "CSV2", "msb": 19, "lsb": 16}, {"name": "State3", "msb": 15, "lsb": 12}, {"name": "State2", "msb": 11, "lsb": 8}, {"name": "State1", "msb": 7, "lsb": 4}, {"name": "State0", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_PFR1_EL1", "fullname": "AArch32 Processor Feature Register 1", "enc": [3, 0, 0, 1, 1], "fieldsets": [{"fields": [{"name": "GIC", "msb": 31, "lsb": 28}, {"name": "Virt_frac", "msb": 27, "lsb": 24}, {"name": "Sec_frac", "msb": 23, "lsb": 20}, {"name": "GenTimer", "msb": 19, "lsb": 16}, {"name": "Virtualization", "msb": 15, "lsb": 12}, {"name": "MProgMod", "msb": 11, "lsb": 8}, {"name": "Security", "msb": 7, "lsb": 4}, {"name": "ProgMod", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "ID_PFR2_EL1", "fullname": "AArch32 Processor Feature Register 2", "enc": [3, 0, 0, 3, 4], "fieldsets": [{"fields": [{"name": "RAS_frac", "msb": 11, "lsb": 8}, {"name": "SSBS", "msb": 7, "lsb": 4}, {"name": "CSV3", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "IFSR32_EL2", "fullname": "Instruction Fault Status Register (EL2)", "enc": [3, 4, 5, 0, 1], "fieldsets": [{"instance": "TTBCR.EAE==0", "fields": [{"name": "FnV", "msb": 16, "lsb": 16}, {"name": "ExT", "msb": 12, "lsb": 12}, {"name": "FS", "msb": 10, "lsb": 10}, {"name": "LPAE", "msb": 9, "lsb": 9}, {"name": "FS[3:0]", "msb": 3, "lsb": 0}]}, {"instance": "TTBCR.EAE==1", "fields": [{"name": "FnV", "msb": 16, "lsb": 16}, {"name": "ExT", "msb": 12, "lsb": 12}, {"name": "LPAE", "msb": 9, "lsb": 9}, {"name": "STATUS", "msb": 5, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ISR_EL1", "fullname": "Interrupt Status Register", "enc": [3, 0, 12, 1, 0], "fieldsets": [{"fields": [{"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}]}], "width": 64}, {"index": 0, "name": "LORC_EL1", "fullname": "LORegion Control (EL1)", "enc": [3, 0, 10, 4, 3], "fieldsets": [{"fields": [{"name": "DS", "msb": 9, "lsb": 2}, {"name": "EN", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "LOREA_EL1", "fullname": "LORegion End Address (EL1)", "enc": [3, 0, 10, 4, 1], "fieldsets": [{"fields": [{"name": "EA[51:48]", "msb": 51, "lsb": 48}, {"name": "EA[47:16]", "msb": 47, "lsb": 16}]}], "width": 64}, {"index": 0, "name": "LORID_EL1", "fullname": "LORegionID (EL1)", "enc": [3, 0, 10, 4, 7], "fieldsets": [{"fields": [{"name": "LD", "msb": 23, "lsb": 16}, {"name": "LR", "msb": 7, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "LORN_EL1", "fullname": "LORegion Number (EL1)", "enc": [3, 0, 10, 4, 2], "fieldsets": [{"fields": [{"name": "Num", "msb": 7, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "LORSA_EL1", "fullname": "LORegion Start Address (EL1)", "enc": [3, 0, 10, 4, 0], "fieldsets": [{"fields": [{"name": "SA", "msb": 51, "lsb": 16}, {"name": "Valid", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MAIR_EL1", "fullname": "Memory Attribute Indirection Register (EL1)", "enc": [3, 0, 10, 2, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "MAIR_EL12", "fullname": "Memory Attribute Indirection Register (EL1)", "enc": [3, 5, 10, 2, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "MAIR_EL1", "fullname": "Memory Attribute Indirection Register (EL2)", "enc": [3, 0, 10, 2, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "MAIR_EL2", "fullname": "Memory Attribute Indirection Register (EL2)", "enc": [3, 4, 10, 2, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "MAIR_EL3", "fullname": "Memory Attribute Indirection Register (EL3)", "enc": [3, 6, 10, 2, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "MDCCINT_EL1", "fullname": "Monitor DCC Interrupt Enable Register", "enc": [2, 0, 0, 2, 0], "fieldsets": [{"fields": [{"name": "RX", "msb": 30, "lsb": 30}, {"name": "TX", "msb": 29, "lsb": 29}]}], "width": 64}, {"index": 0, "name": "MDCCSR_EL0", "fullname": "Monitor DCC Status Register", "enc": [2, 3, 0, 1, 0], "fieldsets": [{"fields": [{"name": "RXfull", "msb": 30, "lsb": 30}, {"name": "TXfull", "msb": 29, "lsb": 29}]}], "width": 64}, {"index": 0, "name": "MDCR_EL2", "fullname": "Monitor Debug Configuration Register (EL2)", "enc": [3, 4, 1, 1, 1], "fieldsets": [{"fields": [{"name": "HPMFZS", "msb": 36, "lsb": 36}, {"name": "HPMFZO", "msb": 29, "lsb": 29}, {"name": "MTPME", "msb": 28, "lsb": 28}, {"name": "TDCC", "msb": 27, "lsb": 27}, {"name": "HLP", "msb": 26, "lsb": 26}, {"name": "HCCD", "msb": 23, "lsb": 23}, {"name": "TTRF", "msb": 19, "lsb": 19}, {"name": "HPMD", "msb": 17, "lsb": 17}, {"name": "HPMD", "msb": 17, "lsb": 17}, {"name": "TPMS", "msb": 14, "lsb": 14}, {"name": "E2PB", "msb": 13, "lsb": 12}, {"name": "TDRA", "msb": 11, "lsb": 11}, {"name": "TDOSA", "msb": 10, "lsb": 10}, {"name": "TDOSA", "msb": 10, "lsb": 10}, {"name": "TDA", "msb": 9, "lsb": 9}, {"name": "TDE", "msb": 8, "lsb": 8}, {"name": "HPME", "msb": 7, "lsb": 7}, {"name": "TPM", "msb": 6, "lsb": 6}, {"name": "TPMCR", "msb": 5, "lsb": 5}, {"name": "HPMN", "msb": 4, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MDCR_EL3", "fullname": "Monitor Debug Configuration Register (EL3)", "enc": [3, 6, 1, 3, 1], "fieldsets": [{"fields": [{"name": "EnPMSN", "msb": 36, "lsb": 36}, {"name": "MPMX", "msb": 35, "lsb": 35}, {"name": "MCCD", "msb": 34, "lsb": 34}, {"name": "MTPME", "msb": 28, "lsb": 28}, {"name": "TDCC", "msb": 27, "lsb": 27}, {"name": "SCCD", "msb": 23, "lsb": 23}, {"name": "EPMAD", "msb": 21, "lsb": 21}, {"name": "EPMAD", "msb": 21, "lsb": 21}, {"name": "EDAD", "msb": 20, "lsb": 20}, {"name": "EDAD", "msb": 20, "lsb": 20}, {"name": "EDAD", "msb": 20, "lsb": 20}, {"name": "TTRF", "msb": 19, "lsb": 19}, {"name": "STE", "msb": 18, "lsb": 18}, {"name": "SPME", "msb": 17, "lsb": 17}, {"name": "SPME", "msb": 17, "lsb": 17}, {"name": "SPME", "msb": 17, "lsb": 17}, {"name": "SDD", "msb": 16, "lsb": 16}, {"name": "SPD32", "msb": 15, "lsb": 14}, {"name": "NSPB", "msb": 13, "lsb": 12}, {"name": "TDOSA", "msb": 10, "lsb": 10}, {"name": "TDOSA", "msb": 10, "lsb": 10}, {"name": "TDA", "msb": 9, "lsb": 9}, {"name": "TPM", "msb": 6, "lsb": 6}]}], "width": 64}, {"index": 0, "name": "MDRAR_EL1", "fullname": "Monitor Debug ROM Address Register", "enc": [2, 0, 1, 0, 0], "fieldsets": [{"fields": [{"name": "ROMADDR", "msb": 51, "lsb": 12}, {"name": "Valid", "msb": 1, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MDSCR_EL1", "fullname": "Monitor Debug System Control Register", "enc": [2, 0, 0, 2, 2], "fieldsets": [{"fields": [{"name": "TFO", "msb": 31, "lsb": 31}, {"name": "RXfull", "msb": 30, "lsb": 30}, {"name": "TXfull", "msb": 29, "lsb": 29}, {"name": "RXO", "msb": 27, "lsb": 27}, {"name": "TXU", "msb": 26, "lsb": 26}, {"name": "INTdis", "msb": 23, "lsb": 22}, {"name": "TDA", "msb": 21, "lsb": 21}, {"name": "SC2", "msb": 19, "lsb": 19}, {"name": "MDE", "msb": 15, "lsb": 15}, {"name": "HDE", "msb": 14, "lsb": 14}, {"name": "KDE", "msb": 13, "lsb": 13}, {"name": "TDCC", "msb": 12, "lsb": 12}, {"name": "ERR", "msb": 6, "lsb": 6}, {"name": "SS", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MIDR_EL1", "fullname": "Main ID Register", "enc": [3, 0, 0, 0, 0], "fieldsets": [{"fields": [{"name": "Implementer", "msb": 31, "lsb": 24}, {"name": "Variant", "msb": 23, "lsb": 20}, {"name": "Architecture", "msb": 19, "lsb": 16}, {"name": "PartNum", "msb": 15, "lsb": 4}, {"name": "Revision", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAM0_EL1", "fullname": "MPAM0 Register (EL1)", "enc": [3, 0, 10, 5, 1], "fieldsets": [{"fields": [{"name": "PMG_D", "msb": 47, "lsb": 40}, {"name": "PMG_I", "msb": 39, "lsb": 32}, {"name": "PARTID_D", "msb": 31, "lsb": 16}, {"name": "PARTID_I", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAM1_EL1", "fullname": "MPAM1 Register (EL1)", "enc": [3, 0, 10, 5, 0], "fieldsets": [{"fields": [{"name": "MPAMEN", "msb": 63, "lsb": 63}, {"name": "FORCED_NS", "msb": 60, "lsb": 60}, {"name": "PMG_D", "msb": 47, "lsb": 40}, {"name": "PMG_I", "msb": 39, "lsb": 32}, {"name": "PARTID_D", "msb": 31, "lsb": 16}, {"name": "PARTID_I", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAM1_EL12", "fullname": "MPAM1 Register (EL1)", "enc": [3, 5, 10, 5, 0], "fieldsets": [{"fields": [{"name": "MPAMEN", "msb": 63, "lsb": 63}, {"name": "FORCED_NS", "msb": 60, "lsb": 60}, {"name": "PMG_D", "msb": 47, "lsb": 40}, {"name": "PMG_I", "msb": 39, "lsb": 32}, {"name": "PARTID_D", "msb": 31, "lsb": 16}, {"name": "PARTID_I", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAM1_EL1", "fullname": "MPAM2 Register (EL2)", "enc": [3, 0, 10, 5, 0], "fieldsets": [{"fields": [{"name": "MPAMEN", "msb": 63, "lsb": 63}, {"name": "TIDR", "msb": 58, "lsb": 58}, {"name": "TRAPMPAM0EL1", "msb": 49, "lsb": 49}, {"name": "TRAPMPAM1EL1", "msb": 48, "lsb": 48}, {"name": "PMG_D", "msb": 47, "lsb": 40}, {"name": "PMG_I", "msb": 39, "lsb": 32}, {"name": "PARTID_D", "msb": 31, "lsb": 16}, {"name": "PARTID_I", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAM2_EL2", "fullname": "MPAM2 Register (EL2)", "enc": [3, 4, 10, 5, 0], "fieldsets": [{"fields": [{"name": "MPAMEN", "msb": 63, "lsb": 63}, {"name": "TIDR", "msb": 58, "lsb": 58}, {"name": "TRAPMPAM0EL1", "msb": 49, "lsb": 49}, {"name": "TRAPMPAM1EL1", "msb": 48, "lsb": 48}, {"name": "PMG_D", "msb": 47, "lsb": 40}, {"name": "PMG_I", "msb": 39, "lsb": 32}, {"name": "PARTID_D", "msb": 31, "lsb": 16}, {"name": "PARTID_I", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAM3_EL3", "fullname": "MPAM3 Register (EL3)", "enc": [3, 6, 10, 5, 0], "fieldsets": [{"fields": [{"name": "MPAMEN", "msb": 63, "lsb": 63}, {"name": "TRAPLOWER", "msb": 62, "lsb": 62}, {"name": "SDEFLT", "msb": 61, "lsb": 61}, {"name": "FORCE_NS", "msb": 60, "lsb": 60}, {"name": "PMG_D", "msb": 47, "lsb": 40}, {"name": "PMG_I", "msb": 39, "lsb": 32}, {"name": "PARTID_D", "msb": 31, "lsb": 16}, {"name": "PARTID_I", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAMHCR_EL2", "fullname": "MPAM Hypervisor Control Register (EL2)", "enc": [3, 4, 10, 4, 0], "fieldsets": [{"fields": [{"name": "TRAP_MPAMIDR_EL1", "msb": 31, "lsb": 31}, {"name": "GSTAPP_PLK", "msb": 8, "lsb": 8}, {"name": "EL1_VPMEN", "msb": 1, "lsb": 1}, {"name": "EL0_VPMEN", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAMIDR_EL1", "fullname": "MPAM ID Register (EL1)", "enc": [3, 0, 10, 4, 4], "fieldsets": [{"fields": [{"name": "HAS_SDEFLT", "msb": 61, "lsb": 61}, {"name": "HAS_FORCE_NS", "msb": 60, "lsb": 60}, {"name": "HAS_TIDR", "msb": 58, "lsb": 58}, {"name": "PMG_MAX", "msb": 39, "lsb": 32}, {"name": "VPMR_MAX", "msb": 20, "lsb": 18}, {"name": "HAS_HCR", "msb": 17, "lsb": 17}, {"name": "PARTID_MAX", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAMVPM0_EL2", "fullname": "MPAM Virtual PARTID Mapping Register 0", "enc": [3, 4, 10, 6, 0], "fieldsets": [{"fields": [{"name": "PhyPARTID3", "msb": 63, "lsb": 48}, {"name": "PhyPARTID2", "msb": 47, "lsb": 32}, {"name": "PhyPARTID1", "msb": 31, "lsb": 16}, {"name": "PhyPARTID0", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAMVPM1_EL2", "fullname": "MPAM Virtual PARTID Mapping Register 1", "enc": [3, 4, 10, 6, 1], "fieldsets": [{"fields": [{"name": "PhyPARTID7", "msb": 63, "lsb": 48}, {"name": "PhyPARTID6", "msb": 47, "lsb": 32}, {"name": "PhyPARTID5", "msb": 31, "lsb": 16}, {"name": "PhyPARTID4", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAMVPM2_EL2", "fullname": "MPAM Virtual PARTID Mapping Register 2", "enc": [3, 4, 10, 6, 2], "fieldsets": [{"fields": [{"name": "PhyPARTID11", "msb": 63, "lsb": 48}, {"name": "PhyPARTID10", "msb": 47, "lsb": 32}, {"name": "PhyPARTID9", "msb": 31, "lsb": 16}, {"name": "PhyPARTID8", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAMVPM3_EL2", "fullname": "MPAM Virtual PARTID Mapping Register 3", "enc": [3, 4, 10, 6, 3], "fieldsets": [{"fields": [{"name": "PhyPARTID15", "msb": 63, "lsb": 48}, {"name": "PhyPARTID14", "msb": 47, "lsb": 32}, {"name": "PhyPARTID13", "msb": 31, "lsb": 16}, {"name": "PhyPARTID12", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAMVPM4_EL2", "fullname": "MPAM Virtual PARTID Mapping Register 4", "enc": [3, 4, 10, 6, 4], "fieldsets": [{"fields": [{"name": "PhyPARTID19", "msb": 63, "lsb": 48}, {"name": "PhyPARTID18", "msb": 47, "lsb": 32}, {"name": "PhyPARTID17", "msb": 31, "lsb": 16}, {"name": "PhyPARTID16", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAMVPM5_EL2", "fullname": "MPAM Virtual PARTID Mapping Register 5", "enc": [3, 4, 10, 6, 5], "fieldsets": [{"fields": [{"name": "PhyPARTID23", "msb": 63, "lsb": 48}, {"name": "PhyPARTID22", "msb": 47, "lsb": 32}, {"name": "PhyPARTID21", "msb": 31, "lsb": 16}, {"name": "PhyPARTID20", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAMVPM6_EL2", "fullname": "MPAM Virtual PARTID Mapping Register 6", "enc": [3, 4, 10, 6, 6], "fieldsets": [{"fields": [{"name": "PhyPARTID27", "msb": 63, "lsb": 48}, {"name": "PhyPARTID26", "msb": 47, "lsb": 32}, {"name": "PhyPARTID25", "msb": 31, "lsb": 16}, {"name": "PhyPARTID24", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAMVPM7_EL2", "fullname": "MPAM Virtual PARTID Mapping Register 7", "enc": [3, 4, 10, 6, 7], "fieldsets": [{"fields": [{"name": "PhyPARTID31", "msb": 63, "lsb": 48}, {"name": "PhyPARTID30", "msb": 47, "lsb": 32}, {"name": "PhyPARTID29", "msb": 31, "lsb": 16}, {"name": "PhyPARTID28", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPAMVPMV_EL2", "fullname": "MPAM Virtual Partition Mapping Valid Register", "enc": [3, 4, 10, 4, 1], "fieldsets": [{"fields": [{"name": "VPM_V<m>", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPIDR_EL1", "fullname": "Multiprocessor Affinity Register", "enc": [3, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "Aff3", "msb": 39, "lsb": 32}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "MT", "msb": 24, "lsb": 24}, {"name": "Aff2", "msb": 23, "lsb": 16}, {"name": "Aff1", "msb": 15, "lsb": 8}, {"name": "Aff0", "msb": 7, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MVFR0_EL1", "fullname": "AArch32 Media and VFP Feature Register 0", "enc": [3, 0, 0, 3, 0], "fieldsets": [{"fields": [{"name": "FPRound", "msb": 31, "lsb": 28}, {"name": "FPShVec", "msb": 27, "lsb": 24}, {"name": "FPSqrt", "msb": 23, "lsb": 20}, {"name": "FPDivide", "msb": 19, "lsb": 16}, {"name": "FPTrap", "msb": 15, "lsb": 12}, {"name": "FPDP", "msb": 11, "lsb": 8}, {"name": "FPSP", "msb": 7, "lsb": 4}, {"name": "SIMDReg", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "MVFR1_EL1", "fullname": "AArch32 Media and VFP Feature Register 1", "enc": [3, 0, 0, 3, 1], "fieldsets": [{"fields": [{"name": "SIMDFMAC", "msb": 31, "lsb": 28}, {"name": "FPHP", "msb": 27, "lsb": 24}, {"name": "SIMDHP", "msb": 23, "lsb": 20}, {"name": "SIMDSP", "msb": 19, "lsb": 16}, {"name": "SIMDInt", "msb": 15, "lsb": 12}, {"name": "SIMDLS", "msb": 11, "lsb": 8}, {"name": "FPDNaN", "msb": 7, "lsb": 4}, {"name": "FPFtZ", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "MVFR2_EL1", "fullname": "AArch32 Media and VFP Feature Register 2", "enc": [3, 0, 0, 3, 2], "fieldsets": [{"fields": [{"name": "FPMisc", "msb": 7, "lsb": 4}, {"name": "SIMDMisc", "msb": 3, "lsb": 0}]}, {"fields": []}], "width": 64}, {"index": 0, "name": "NZCV", "fullname": "Condition Flags", "enc": [3, 3, 4, 2, 0], "fieldsets": [{"fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}]}], "width": 64}, {"index": 0, "name": "OSDLR_EL1", "fullname": "OS Double Lock Register", "enc": [2, 0, 1, 3, 4], "fieldsets": [{"fields": [{"name": "DLK", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "OSDTRRX_EL1", "fullname": "OS Lock Data Transfer Register, Receive", "enc": [2, 0, 0, 0, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "OSDTRTX_EL1", "fullname": "OS Lock Data Transfer Register, Transmit", "enc": [2, 0, 0, 3, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "OSECCR_EL1", "fullname": "OS Lock Exception Catch Control Register", "enc": [2, 0, 0, 6, 2], "fieldsets": [{"instance": "OSLSR_EL1.OSLK == 1", "fields": [{"name": "EDECCR", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "OSLAR_EL1", "fullname": "OS Lock Access Register", "enc": [2, 0, 1, 0, 4], "fieldsets": [{"fields": [{"name": "OSLK", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "OSLSR_EL1", "fullname": "OS Lock Status Register", "enc": [2, 0, 1, 1, 4], "fieldsets": [{"fields": [{"name": "OSLM", "msb": 3, "lsb": 3}, {"name": "nTT", "msb": 2, "lsb": 2}, {"name": "OSLK", "msb": 1, "lsb": 1}, {"name": "OSLM[0]", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PAN", "fullname": "Privileged Access Never", "enc": [3, 0, 4, 2, 3], "fieldsets": [{"fields": [{"name": "PAN", "msb": 22, "lsb": 22}]}], "width": 64}, {"index": 0, "name": "PAR_EL1", "fullname": "Physical Address Register", "enc": [3, 0, 7, 4, 0], "fieldsets": [{"instance": "AArch64-PAR_EL1.F == 0b0", "fields": [{"name": "ATTR", "msb": 63, "lsb": 56}, {"name": "PA[51:48]", "msb": 51, "lsb": 48}, {"name": "PA[47:12]", "msb": 47, "lsb": 12}, {"name": "IMPLEMENTATION DEFINED", "msb": 10, "lsb": 10}, {"name": "NS", "msb": 9, "lsb": 9}, {"name": "SH", "msb": 8, "lsb": 7}, {"name": "F", "msb": 0, "lsb": 0}]}, {"instance": "AArch64-PAR_EL1.F == 0b1", "fields": [{"name": "IMPLEMENTATION DEFINED", "msb": 63, "lsb": 56}, {"name": "IMPLEMENTATION DEFINED", "msb": 55, "lsb": 52}, {"name": "IMPLEMENTATION DEFINED", "msb": 51, "lsb": 48}, {"name": "S", "msb": 9, "lsb": 9}, {"name": "PTW", "msb": 8, "lsb": 8}, {"name": "FST", "msb": 6, "lsb": 1}, {"name": "F", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMBIDR_EL1", "fullname": "Profiling Buffer ID Register", "enc": [3, 0, 9, 10, 7], "fieldsets": [{"fields": [{"name": "F", "msb": 5, "lsb": 5}, {"name": "P", "msb": 4, "lsb": 4}, {"name": "Align", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMBLIMITR_EL1", "fullname": "Profiling Buffer Limit Address Register", "enc": [3, 0, 9, 10, 0], "fieldsets": [{"fields": [{"name": "LIMIT", "msb": 63, "lsb": 12}, {"name": "PMFZ", "msb": 5, "lsb": 5}, {"name": "FM", "msb": 2, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMBPTR_EL1", "fullname": "Profiling Buffer Write Pointer Register", "enc": [3, 0, 9, 10, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "PMBSR_EL1", "fullname": "Profiling Buffer Status/syndrome Register", "enc": [3, 0, 9, 10, 3], "fieldsets": [{"fields": [{"name": "EC", "msb": 31, "lsb": 26}, {"name": "DL", "msb": 19, "lsb": 19}, {"name": "EA", "msb": 18, "lsb": 18}, {"name": "S", "msb": 17, "lsb": 17}, {"name": "COLL", "msb": 16, "lsb": 16}, {"name": "MSS", "msb": 15, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMCCFILTR_EL0", "fullname": "Performance Monitors Cycle Count Filter Register", "enc": [3, 3, 14, 15, 7], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "SH", "msb": 24, "lsb": 24}]}], "width": 64}, {"index": 0, "name": "PMCCNTR_EL0", "fullname": "Performance Monitors Cycle Count Register", "enc": [3, 3, 9, 13, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "PMCEID0_EL0", "fullname": "Performance Monitors Common Event Identification register 0", "enc": [3, 3, 9, 12, 6], "fieldsets": [{"fields": [{"name": "IDhi<n>", "msb": 63, "lsb": 32}, {"name": "ID<n>", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMCEID1_EL0", "fullname": "Performance Monitors Common Event Identification register 1", "enc": [3, 3, 9, 12, 7], "fieldsets": [{"fields": [{"name": "IDhi<n>", "msb": 63, "lsb": 32}, {"name": "ID<n>", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMCNTENCLR_EL0", "fullname": "Performance Monitors Count Enable Clear register", "enc": [3, 3, 9, 12, 2], "fieldsets": [{"fields": [{"name": "C", "msb": 31, "lsb": 31}, {"name": "P<n>", "msb": 30, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMCNTENSET_EL0", "fullname": "Performance Monitors Count Enable Set register", "enc": [3, 3, 9, 12, 1], "fieldsets": [{"fields": [{"name": "C", "msb": 31, "lsb": 31}, {"name": "P<n>", "msb": 30, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMCR_EL0", "fullname": "Performance Monitors Control Register", "enc": [3, 3, 9, 12, 0], "fieldsets": [{"fields": [{"name": "FZS", "msb": 32, "lsb": 32}, {"name": "IMP", "msb": 31, "lsb": 24}, {"name": "IDCODE", "msb": 23, "lsb": 16}, {"name": "N", "msb": 15, "lsb": 11}, {"name": "FZO", "msb": 9, "lsb": 9}, {"name": "LP", "msb": 7, "lsb": 7}, {"name": "LC", "msb": 6, "lsb": 6}, {"name": "DP", "msb": 5, "lsb": 5}, {"name": "X", "msb": 4, "lsb": 4}, {"name": "D", "msb": 3, "lsb": 3}, {"name": "C", "msb": 2, "lsb": 2}, {"name": "P", "msb": 1, "lsb": 1}, {"name": "E", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMEVCNTR0_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 1, "name": "PMEVCNTR1_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 2, "name": "PMEVCNTR2_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 3, "name": "PMEVCNTR3_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 4, "name": "PMEVCNTR4_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 5, "name": "PMEVCNTR5_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 6, "name": "PMEVCNTR6_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 7, "name": "PMEVCNTR7_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 8, "name": "PMEVCNTR8_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 9, "name": "PMEVCNTR9_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 10, "name": "PMEVCNTR10_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 11, "name": "PMEVCNTR11_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 12, "name": "PMEVCNTR12_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 13, "name": "PMEVCNTR13_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 14, "name": "PMEVCNTR14_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 15, "name": "PMEVCNTR15_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 16, "name": "PMEVCNTR16_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 17, "name": "PMEVCNTR17_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 18, "name": "PMEVCNTR18_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 19, "name": "PMEVCNTR19_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 20, "name": "PMEVCNTR20_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 21, "name": "PMEVCNTR21_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 22, "name": "PMEVCNTR22_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 23, "name": "PMEVCNTR23_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 24, "name": "PMEVCNTR24_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 25, "name": "PMEVCNTR25_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 26, "name": "PMEVCNTR26_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 27, "name": "PMEVCNTR27_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 28, "name": "PMEVCNTR28_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 29, "name": "PMEVCNTR29_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 30, "name": "PMEVCNTR30_EL0", "fullname": "Performance Monitors Event Count Registers", "enc": [3, 3, 14, 8, 0], "fieldsets": [{"fields": []}, {"fields": []}], "width": 64}, {"index": 0, "name": "PMEVTYPER0_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 1, "name": "PMEVTYPER1_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 2, "name": "PMEVTYPER2_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 3, "name": "PMEVTYPER3_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 4, "name": "PMEVTYPER4_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 5, "name": "PMEVTYPER5_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 6, "name": "PMEVTYPER6_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 7, "name": "PMEVTYPER7_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 8, "name": "PMEVTYPER8_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 9, "name": "PMEVTYPER9_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 10, "name": "PMEVTYPER10_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 11, "name": "PMEVTYPER11_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 12, "name": "PMEVTYPER12_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 13, "name": "PMEVTYPER13_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 14, "name": "PMEVTYPER14_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 15, "name": "PMEVTYPER15_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 16, "name": "PMEVTYPER16_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 17, "name": "PMEVTYPER17_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 18, "name": "PMEVTYPER18_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 19, "name": "PMEVTYPER19_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 20, "name": "PMEVTYPER20_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 21, "name": "PMEVTYPER21_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 22, "name": "PMEVTYPER22_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 23, "name": "PMEVTYPER23_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 24, "name": "PMEVTYPER24_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 25, "name": "PMEVTYPER25_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 26, "name": "PMEVTYPER26_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 27, "name": "PMEVTYPER27_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 28, "name": "PMEVTYPER28_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 29, "name": "PMEVTYPER29_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 30, "name": "PMEVTYPER30_EL0", "fullname": "Performance Monitors Event Type Registers", "enc": [3, 3, 14, 12, 0], "fieldsets": [{"fields": [{"name": "P", "msb": 31, "lsb": 31}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "NSK", "msb": 29, "lsb": 29}, {"name": "NSU", "msb": 28, "lsb": 28}, {"name": "NSH", "msb": 27, "lsb": 27}, {"name": "M", "msb": 26, "lsb": 26}, {"name": "MT", "msb": 25, "lsb": 25}, {"name": "SH", "msb": 24, "lsb": 24}, {"name": "evtCount[15:10]", "msb": 15, "lsb": 10}, {"name": "evtCount[9:0]", "msb": 9, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMINTENCLR_EL1", "fullname": "Performance Monitors Interrupt Enable Clear register", "enc": [3, 0, 9, 14, 2], "fieldsets": [{"fields": [{"name": "C", "msb": 31, "lsb": 31}, {"name": "P<n>", "msb": 30, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMINTENSET_EL1", "fullname": "Performance Monitors Interrupt Enable Set register", "enc": [3, 0, 9, 14, 1], "fieldsets": [{"fields": [{"name": "C", "msb": 31, "lsb": 31}, {"name": "P<n>", "msb": 30, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMMIR_EL1", "fullname": "Performance Monitors Machine Identification Register", "enc": [3, 0, 9, 14, 6], "fieldsets": [{"fields": [{"name": "BUS_WIDTH", "msb": 19, "lsb": 16}, {"name": "BUS_SLOTS", "msb": 15, "lsb": 8}, {"name": "SLOTS", "msb": 7, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMOVSCLR_EL0", "fullname": "Performance Monitors Overflow Flag Status Clear Register", "enc": [3, 3, 9, 12, 3], "fieldsets": [{"fields": [{"name": "C", "msb": 31, "lsb": 31}, {"name": "P<n>", "msb": 30, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMOVSSET_EL0", "fullname": "Performance Monitors Overflow Flag Status Set register", "enc": [3, 3, 9, 14, 3], "fieldsets": [{"fields": [{"name": "C", "msb": 31, "lsb": 31}, {"name": "P<n>", "msb": 30, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMSCR_EL1", "fullname": "Statistical Profiling Control Register (EL1)", "enc": [3, 0, 9, 9, 0], "fieldsets": [{"fields": [{"name": "PCT", "msb": 7, "lsb": 6}, {"name": "PCT", "msb": 7, "lsb": 6}, {"name": "TS", "msb": 5, "lsb": 5}, {"name": "PA", "msb": 4, "lsb": 4}, {"name": "CX", "msb": 3, "lsb": 3}, {"name": "E1SPE", "msb": 1, "lsb": 1}, {"name": "E0SPE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMSCR_EL12", "fullname": "Statistical Profiling Control Register (EL1)", "enc": [3, 5, 9, 9, 0], "fieldsets": [{"fields": [{"name": "PCT", "msb": 7, "lsb": 6}, {"name": "PCT", "msb": 7, "lsb": 6}, {"name": "TS", "msb": 5, "lsb": 5}, {"name": "PA", "msb": 4, "lsb": 4}, {"name": "CX", "msb": 3, "lsb": 3}, {"name": "E1SPE", "msb": 1, "lsb": 1}, {"name": "E0SPE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMSCR_EL1", "fullname": "Statistical Profiling Control Register (EL2)", "enc": [3, 0, 9, 9, 0], "fieldsets": [{"fields": [{"name": "PCT", "msb": 7, "lsb": 6}, {"name": "TS", "msb": 5, "lsb": 5}, {"name": "PA", "msb": 4, "lsb": 4}, {"name": "CX", "msb": 3, "lsb": 3}, {"name": "E2SPE", "msb": 1, "lsb": 1}, {"name": "E0HSPE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMSCR_EL2", "fullname": "Statistical Profiling Control Register (EL2)", "enc": [3, 4, 9, 9, 0], "fieldsets": [{"fields": [{"name": "PCT", "msb": 7, "lsb": 6}, {"name": "TS", "msb": 5, "lsb": 5}, {"name": "PA", "msb": 4, "lsb": 4}, {"name": "CX", "msb": 3, "lsb": 3}, {"name": "E2SPE", "msb": 1, "lsb": 1}, {"name": "E0HSPE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMSELR_EL0", "fullname": "Performance Monitors Event Counter Selection Register", "enc": [3, 3, 9, 12, 5], "fieldsets": [{"fields": [{"name": "SEL", "msb": 4, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMSEVFR_EL1", "fullname": "Sampling Event Filter Register", "enc": [3, 0, 9, 9, 5], "fieldsets": [{"fields": [{"name": "E[63]", "msb": 63, "lsb": 63}, {"name": "E[62]", "msb": 62, "lsb": 62}, {"name": "E[61]", "msb": 61, "lsb": 61}, {"name": "E[60]", "msb": 60, "lsb": 60}, {"name": "E[59]", "msb": 59, "lsb": 59}, {"name": "E[58]", "msb": 58, "lsb": 58}, {"name": "E[57]", "msb": 57, "lsb": 57}, {"name": "E[56]", "msb": 56, "lsb": 56}, {"name": "E[55]", "msb": 55, "lsb": 55}, {"name": "E[54]", "msb": 54, "lsb": 54}, {"name": "E[53]", "msb": 53, "lsb": 53}, {"name": "E[52]", "msb": 52, "lsb": 52}, {"name": "E[51]", "msb": 51, "lsb": 51}, {"name": "E[50]", "msb": 50, "lsb": 50}, {"name": "E[49]", "msb": 49, "lsb": 49}, {"name": "E[<x>]", "msb": 63, "lsb": 48}, {"name": "E[48]", "msb": 48, "lsb": 48}, {"name": "E[31]", "msb": 31, "lsb": 31}, {"name": "E[30]", "msb": 30, "lsb": 30}, {"name": "E[29]", "msb": 29, "lsb": 29}, {"name": "E[28]", "msb": 28, "lsb": 28}, {"name": "E[27]", "msb": 27, "lsb": 27}, {"name": "E[26]", "msb": 26, "lsb": 26}, {"name": "E[25]", "msb": 25, "lsb": 25}, {"name": "E[24]", "msb": 24, "lsb": 24}, {"name": "E[18]", "msb": 18, "lsb": 18}, {"name": "E[17]", "msb": 17, "lsb": 17}, {"name": "E[15]", "msb": 15, "lsb": 15}, {"name": "E[14]", "msb": 14, "lsb": 14}, {"name": "E[13]", "msb": 13, "lsb": 13}, {"name": "E[12]", "msb": 12, "lsb": 12}, {"name": "E[11]", "msb": 11, "lsb": 11}, {"name": "E[7]", "msb": 7, "lsb": 7}, {"name": "E[6]", "msb": 6, "lsb": 6}, {"name": "E[5]", "msb": 5, "lsb": 5}, {"name": "E[3]", "msb": 3, "lsb": 3}, {"name": "E[1]", "msb": 1, "lsb": 1}]}], "width": 64}, {"index": 0, "name": "PMSFCR_EL1", "fullname": "Sampling Filter Control Register", "enc": [3, 0, 9, 9, 4], "fieldsets": [{"fields": [{"name": "ST", "msb": 18, "lsb": 18}, {"name": "LD", "msb": 17, "lsb": 17}, {"name": "B", "msb": 16, "lsb": 16}, {"name": "FnE", "msb": 3, "lsb": 3}, {"name": "FL", "msb": 2, "lsb": 2}, {"name": "FT", "msb": 1, "lsb": 1}, {"name": "FE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMSICR_EL1", "fullname": "Sampling Interval Counter Register", "enc": [3, 0, 9, 9, 2], "fieldsets": [{"fields": [{"name": "ECOUNT", "msb": 63, "lsb": 56}, {"name": "COUNT", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMSIDR_EL1", "fullname": "Sampling Profiling ID Register", "enc": [3, 0, 9, 9, 7], "fieldsets": [{"fields": [{"name": "Format", "msb": 23, "lsb": 20}, {"name": "CountSize", "msb": 19, "lsb": 16}, {"name": "MaxSize", "msb": 15, "lsb": 12}, {"name": "Interval", "msb": 11, "lsb": 8}, {"name": "FnE", "msb": 6, "lsb": 6}, {"name": "ERnd", "msb": 5, "lsb": 5}, {"name": "LDS", "msb": 4, "lsb": 4}, {"name": "ArchInst", "msb": 3, "lsb": 3}, {"name": "FL", "msb": 2, "lsb": 2}, {"name": "FT", "msb": 1, "lsb": 1}, {"name": "FE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMSIRR_EL1", "fullname": "Sampling Interval Reload Register", "enc": [3, 0, 9, 9, 3], "fieldsets": [{"fields": [{"name": "INTERVAL", "msb": 31, "lsb": 8}, {"name": "RND", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMSLATFR_EL1", "fullname": "Sampling Latency Filter Register", "enc": [3, 0, 9, 9, 6], "fieldsets": [{"fields": [{"name": "MINLAT", "msb": 11, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMSNEVFR_EL1", "fullname": "Sampling Inverted Event Filter Register", "enc": [3, 0, 9, 9, 1], "fieldsets": [{"instance": "PMSNEVFR_EL1", "fields": [{"name": "E[63]", "msb": 63, "lsb": 63}, {"name": "E[62]", "msb": 62, "lsb": 62}, {"name": "E[61]", "msb": 61, "lsb": 61}, {"name": "E[60]", "msb": 60, "lsb": 60}, {"name": "E[59]", "msb": 59, "lsb": 59}, {"name": "E[58]", "msb": 58, "lsb": 58}, {"name": "E[57]", "msb": 57, "lsb": 57}, {"name": "E[56]", "msb": 56, "lsb": 56}, {"name": "E[55]", "msb": 55, "lsb": 55}, {"name": "E[54]", "msb": 54, "lsb": 54}, {"name": "E[53]", "msb": 53, "lsb": 53}, {"name": "E[52]", "msb": 52, "lsb": 52}, {"name": "E[51]", "msb": 51, "lsb": 51}, {"name": "E[50]", "msb": 50, "lsb": 50}, {"name": "E[49]", "msb": 49, "lsb": 49}, {"name": "E[<x>]", "msb": 63, "lsb": 48}, {"name": "E[48]", "msb": 48, "lsb": 48}, {"name": "E[31]", "msb": 31, "lsb": 31}, {"name": "E[30]", "msb": 30, "lsb": 30}, {"name": "E[29]", "msb": 29, "lsb": 29}, {"name": "E[28]", "msb": 28, "lsb": 28}, {"name": "E[27]", "msb": 27, "lsb": 27}, {"name": "E[26]", "msb": 26, "lsb": 26}, {"name": "E[25]", "msb": 25, "lsb": 25}, {"name": "E[24]", "msb": 24, "lsb": 24}, {"name": "E[18]", "msb": 18, "lsb": 18}, {"name": "E[17]", "msb": 17, "lsb": 17}, {"name": "E[15]", "msb": 15, "lsb": 15}, {"name": "E[14]", "msb": 14, "lsb": 14}, {"name": "E[13]", "msb": 13, "lsb": 13}, {"name": "E[12]", "msb": 12, "lsb": 12}, {"name": "E[11]", "msb": 11, "lsb": 11}, {"name": "E[7]", "msb": 7, "lsb": 7}, {"name": "E[6]", "msb": 6, "lsb": 6}, {"name": "E[5]", "msb": 5, "lsb": 5}, {"name": "E[3]", "msb": 3, "lsb": 3}, {"name": "E[1]", "msb": 1, "lsb": 1}]}], "width": 64}, {"index": 0, "name": "PMSWINC_EL0", "fullname": "Performance Monitors Software Increment register", "enc": [3, 3, 9, 12, 4], "fieldsets": [{"fields": [{"name": "P<n>", "msb": 30, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMUSERENR_EL0", "fullname": "Performance Monitors User Enable Register", "enc": [3, 3, 9, 14, 0], "fieldsets": [{"fields": [{"name": "ER", "msb": 3, "lsb": 3}, {"name": "CR", "msb": 2, "lsb": 2}, {"name": "SW", "msb": 1, "lsb": 1}, {"name": "EN", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMXEVCNTR_EL0", "fullname": "Performance Monitors Selected Event Count Register", "enc": [3, 3, 9, 13, 2], "fieldsets": [{"fields": []}, {"fields": [{"name": "PMEVCNTR<n>", "msb": 31, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "PMXEVTYPER_EL0", "fullname": "Performance Monitors Selected Event Type Register", "enc": [3, 3, 9, 13, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "REVIDR_EL1", "fullname": "Revision ID Register", "enc": [3, 0, 0, 0, 6], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "RGSR_EL1", "fullname": "Random Allocation Tag Seed Register.", "enc": [3, 0, 1, 0, 5], "fieldsets": [{"fields": [{"name": "SEED", "msb": 23, "lsb": 8}, {"name": "TAG", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "RMR_EL1", "fullname": "Reset Management Register (EL1)", "enc": [3, 0, 12, 0, 2], "fieldsets": [{"fields": [{"name": "RR", "msb": 1, "lsb": 1}, {"name": "AA64", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "RMR_EL2", "fullname": "Reset Management Register (EL2)", "enc": [3, 4, 12, 0, 2], "fieldsets": [{"fields": [{"name": "RR", "msb": 1, "lsb": 1}, {"name": "AA64", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "RMR_EL3", "fullname": "Reset Management Register (EL3)", "enc": [3, 6, 12, 0, 2], "fieldsets": [{"fields": [{"name": "RR", "msb": 1, "lsb": 1}, {"name": "AA64", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "RNDRRS", "fullname": "Reseeded Random Number", "enc": [3, 3, 2, 4, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "RNDR", "fullname": "Random Number", "enc": [3, 3, 2, 4, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "RVBAR_EL1", "fullname": "Reset Vector Base Address Register (if EL2 and EL3 not implemented)", "enc": [3, 0, 12, 0, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "RVBAR_EL2", "fullname": "Reset Vector Base Address Register (if EL3 not implemented)", "enc": [3, 4, 12, 0, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "RVBAR_EL3", "fullname": "Reset Vector Base Address Register (if EL3 implemented)", "enc": [3, 6, 12, 0, 1], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "SCR_EL3", "fullname": "Secure Configuration Register", "enc": [3, 6, 1, 1, 0], "fieldsets": [{"fields": [{"name": "HXEn", "msb": 38, "lsb": 38}, {"name": "ADEn", "msb": 37, "lsb": 37}, {"name": "EnAS0", "msb": 36, "lsb": 36}, {"name": "AMVOFFEN", "msb": 35, "lsb": 35}, {"name": "TWEDEL", "msb": 33, "lsb": 30}, {"name": "TWEDEn", "msb": 29, "lsb": 29}, {"name": "ECVEn", "msb": 28, "lsb": 28}, {"name": "FGTEn", "msb": 27, "lsb": 27}, {"name": "ATA", "msb": 26, "lsb": 26}, {"name": "EnSCXT", "msb": 25, "lsb": 25}, {"name": "FIEN", "msb": 21, "lsb": 21}, {"name": "NMEA", "msb": 20, "lsb": 20}, {"name": "EASE", "msb": 19, "lsb": 19}, {"name": "EEL2", "msb": 18, "lsb": 18}, {"name": "API", "msb": 17, "lsb": 17}, {"name": "API", "msb": 17, "lsb": 17}, {"name": "APK", "msb": 16, "lsb": 16}, {"name": "TERR", "msb": 15, "lsb": 15}, {"name": "TLOR", "msb": 14, "lsb": 14}, {"name": "TWE", "msb": 13, "lsb": 13}, {"name": "TWI", "msb": 12, "lsb": 12}, {"name": "ST", "msb": 11, "lsb": 11}, {"name": "RW", "msb": 10, "lsb": 10}, {"name": "SIF", "msb": 9, "lsb": 9}, {"name": "SIF", "msb": 9, "lsb": 9}, {"name": "HCE", "msb": 8, "lsb": 8}, {"name": "SMD", "msb": 7, "lsb": 7}, {"name": "EA", "msb": 3, "lsb": 3}, {"name": "FIQ", "msb": 2, "lsb": 2}, {"name": "IRQ", "msb": 1, "lsb": 1}, {"name": "NS", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SCTLR_EL1", "fullname": "System Control Register (EL1)", "enc": [3, 0, 1, 0, 0], "fieldsets": [{"fields": [{"name": "EPAN", "msb": 57, "lsb": 57}, {"name": "EnALS", "msb": 56, "lsb": 56}, {"name": "EnAS0", "msb": 55, "lsb": 55}, {"name": "EnASR", "msb": 54, "lsb": 54}, {"name": "TWEDEL", "msb": 49, "lsb": 46}, {"name": "TWEDEn", "msb": 45, "lsb": 45}, {"name": "DSSBS", "msb": 44, "lsb": 44}, {"name": "ATA", "msb": 43, "lsb": 43}, {"name": "ATA0", "msb": 42, "lsb": 42}, {"name": "TCF", "msb": 41, "lsb": 40}, {"name": "TCF0", "msb": 39, "lsb": 38}, {"name": "ITFSB", "msb": 37, "lsb": 37}, {"name": "BT1", "msb": 36, "lsb": 36}, {"name": "BT0", "msb": 35, "lsb": 35}, {"name": "EnIA", "msb": 31, "lsb": 31}, {"name": "EnIB", "msb": 30, "lsb": 30}, {"name": "LSMAOE", "msb": 29, "lsb": 29}, {"name": "nTLSMD", "msb": 28, "lsb": 28}, {"name": "EnDA", "msb": 27, "lsb": 27}, {"name": "UCI", "msb": 26, "lsb": 26}, {"name": "EE", "msb": 25, "lsb": 25}, {"name": "E0E", "msb": 24, "lsb": 24}, {"name": "SPAN", "msb": 23, "lsb": 23}, {"name": "EIS", "msb": 22, "lsb": 22}, {"name": "IESB", "msb": 21, "lsb": 21}, {"name": "TSCXT", "msb": 20, "lsb": 20}, {"name": "WXN", "msb": 19, "lsb": 19}, {"name": "nTWE", "msb": 18, "lsb": 18}, {"name": "nTWI", "msb": 16, "lsb": 16}, {"name": "UCT", "msb": 15, "lsb": 15}, {"name": "DZE", "msb": 14, "lsb": 14}, {"name": "EnDB", "msb": 13, "lsb": 13}, {"name": "I", "msb": 12, "lsb": 12}, {"name": "EOS", "msb": 11, "lsb": 11}, {"name": "EnRCTX", "msb": 10, "lsb": 10}, {"name": "UMA", "msb": 9, "lsb": 9}, {"name": "SED", "msb": 8, "lsb": 8}, {"name": "ITD", "msb": 7, "lsb": 7}, {"name": "nAA", "msb": 6, "lsb": 6}, {"name": "CP15BEN", "msb": 5, "lsb": 5}, {"name": "SA0", "msb": 4, "lsb": 4}, {"name": "SA", "msb": 3, "lsb": 3}, {"name": "C", "msb": 2, "lsb": 2}, {"name": "A", "msb": 1, "lsb": 1}, {"name": "M", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SCTLR_EL12", "fullname": "System Control Register (EL1)", "enc": [3, 5, 1, 0, 0], "fieldsets": [{"fields": [{"name": "EPAN", "msb": 57, "lsb": 57}, {"name": "EnALS", "msb": 56, "lsb": 56}, {"name": "EnAS0", "msb": 55, "lsb": 55}, {"name": "EnASR", "msb": 54, "lsb": 54}, {"name": "TWEDEL", "msb": 49, "lsb": 46}, {"name": "TWEDEn", "msb": 45, "lsb": 45}, {"name": "DSSBS", "msb": 44, "lsb": 44}, {"name": "ATA", "msb": 43, "lsb": 43}, {"name": "ATA0", "msb": 42, "lsb": 42}, {"name": "TCF", "msb": 41, "lsb": 40}, {"name": "TCF0", "msb": 39, "lsb": 38}, {"name": "ITFSB", "msb": 37, "lsb": 37}, {"name": "BT1", "msb": 36, "lsb": 36}, {"name": "BT0", "msb": 35, "lsb": 35}, {"name": "EnIA", "msb": 31, "lsb": 31}, {"name": "EnIB", "msb": 30, "lsb": 30}, {"name": "LSMAOE", "msb": 29, "lsb": 29}, {"name": "nTLSMD", "msb": 28, "lsb": 28}, {"name": "EnDA", "msb": 27, "lsb": 27}, {"name": "UCI", "msb": 26, "lsb": 26}, {"name": "EE", "msb": 25, "lsb": 25}, {"name": "E0E", "msb": 24, "lsb": 24}, {"name": "SPAN", "msb": 23, "lsb": 23}, {"name": "EIS", "msb": 22, "lsb": 22}, {"name": "IESB", "msb": 21, "lsb": 21}, {"name": "TSCXT", "msb": 20, "lsb": 20}, {"name": "WXN", "msb": 19, "lsb": 19}, {"name": "nTWE", "msb": 18, "lsb": 18}, {"name": "nTWI", "msb": 16, "lsb": 16}, {"name": "UCT", "msb": 15, "lsb": 15}, {"name": "DZE", "msb": 14, "lsb": 14}, {"name": "EnDB", "msb": 13, "lsb": 13}, {"name": "I", "msb": 12, "lsb": 12}, {"name": "EOS", "msb": 11, "lsb": 11}, {"name": "EnRCTX", "msb": 10, "lsb": 10}, {"name": "UMA", "msb": 9, "lsb": 9}, {"name": "SED", "msb": 8, "lsb": 8}, {"name": "ITD", "msb": 7, "lsb": 7}, {"name": "nAA", "msb": 6, "lsb": 6}, {"name": "CP15BEN", "msb": 5, "lsb": 5}, {"name": "SA0", "msb": 4, "lsb": 4}, {"name": "SA", "msb": 3, "lsb": 3}, {"name": "C", "msb": 2, "lsb": 2}, {"name": "A", "msb": 1, "lsb": 1}, {"name": "M", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SCTLR_EL1", "fullname": "System Control Register (EL2)", "enc": [3, 0, 1, 0, 0], "fieldsets": [{"fields": [{"name": "EPAN", "msb": 57, "lsb": 57}, {"name": "EnALS", "msb": 56, "lsb": 56}, {"name": "EnAS0", "msb": 55, "lsb": 55}, {"name": "EnASR", "msb": 54, "lsb": 54}, {"name": "TWEDEL", "msb": 49, "lsb": 46}, {"name": "TWEDEn", "msb": 45, "lsb": 45}, {"name": "DSSBS", "msb": 44, "lsb": 44}, {"name": "ATA", "msb": 43, "lsb": 43}, {"name": "ATA0", "msb": 42, "lsb": 42}, {"name": "TCF", "msb": 41, "lsb": 40}, {"name": "TCF0", "msb": 39, "lsb": 38}, {"name": "ITFSB", "msb": 37, "lsb": 37}, {"name": "BT", "msb": 36, "lsb": 36}, {"name": "BT0", "msb": 35, "lsb": 35}, {"name": "EnIA", "msb": 31, "lsb": 31}, {"name": "EnIB", "msb": 30, "lsb": 30}, {"name": "LSMAOE", "msb": 29, "lsb": 29}, {"name": "nTLSMD", "msb": 28, "lsb": 28}, {"name": "EnDA", "msb": 27, "lsb": 27}, {"name": "UCI", "msb": 26, "lsb": 26}, {"name": "EE", "msb": 25, "lsb": 25}, {"name": "E0E", "msb": 24, "lsb": 24}, {"name": "SPAN", "msb": 23, "lsb": 23}, {"name": "EIS", "msb": 22, "lsb": 22}, {"name": "IESB", "msb": 21, "lsb": 21}, {"name": "TSCXT", "msb": 20, "lsb": 20}, {"name": "WXN", "msb": 19, "lsb": 19}, {"name": "nTWE", "msb": 18, "lsb": 18}, {"name": "nTWI", "msb": 16, "lsb": 16}, {"name": "UCT", "msb": 15, "lsb": 15}, {"name": "DZE", "msb": 14, "lsb": 14}, {"name": "EnDB", "msb": 13, "lsb": 13}, {"name": "I", "msb": 12, "lsb": 12}, {"name": "EOS", "msb": 11, "lsb": 11}, {"name": "EnRCTX", "msb": 10, "lsb": 10}, {"name": "SED", "msb": 8, "lsb": 8}, {"name": "ITD", "msb": 7, "lsb": 7}, {"name": "nAA", "msb": 6, "lsb": 6}, {"name": "CP15BEN", "msb": 5, "lsb": 5}, {"name": "SA0", "msb": 4, "lsb": 4}, {"name": "SA", "msb": 3, "lsb": 3}, {"name": "C", "msb": 2, "lsb": 2}, {"name": "A", "msb": 1, "lsb": 1}, {"name": "M", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SCTLR_EL2", "fullname": "System Control Register (EL2)", "enc": [3, 4, 1, 0, 0], "fieldsets": [{"fields": [{"name": "EPAN", "msb": 57, "lsb": 57}, {"name": "EnALS", "msb": 56, "lsb": 56}, {"name": "EnAS0", "msb": 55, "lsb": 55}, {"name": "EnASR", "msb": 54, "lsb": 54}, {"name": "TWEDEL", "msb": 49, "lsb": 46}, {"name": "TWEDEn", "msb": 45, "lsb": 45}, {"name": "DSSBS", "msb": 44, "lsb": 44}, {"name": "ATA", "msb": 43, "lsb": 43}, {"name": "ATA0", "msb": 42, "lsb": 42}, {"name": "TCF", "msb": 41, "lsb": 40}, {"name": "TCF0", "msb": 39, "lsb": 38}, {"name": "ITFSB", "msb": 37, "lsb": 37}, {"name": "BT", "msb": 36, "lsb": 36}, {"name": "BT0", "msb": 35, "lsb": 35}, {"name": "EnIA", "msb": 31, "lsb": 31}, {"name": "EnIB", "msb": 30, "lsb": 30}, {"name": "LSMAOE", "msb": 29, "lsb": 29}, {"name": "nTLSMD", "msb": 28, "lsb": 28}, {"name": "EnDA", "msb": 27, "lsb": 27}, {"name": "UCI", "msb": 26, "lsb": 26}, {"name": "EE", "msb": 25, "lsb": 25}, {"name": "E0E", "msb": 24, "lsb": 24}, {"name": "SPAN", "msb": 23, "lsb": 23}, {"name": "EIS", "msb": 22, "lsb": 22}, {"name": "IESB", "msb": 21, "lsb": 21}, {"name": "TSCXT", "msb": 20, "lsb": 20}, {"name": "WXN", "msb": 19, "lsb": 19}, {"name": "nTWE", "msb": 18, "lsb": 18}, {"name": "nTWI", "msb": 16, "lsb": 16}, {"name": "UCT", "msb": 15, "lsb": 15}, {"name": "DZE", "msb": 14, "lsb": 14}, {"name": "EnDB", "msb": 13, "lsb": 13}, {"name": "I", "msb": 12, "lsb": 12}, {"name": "EOS", "msb": 11, "lsb": 11}, {"name": "EnRCTX", "msb": 10, "lsb": 10}, {"name": "SED", "msb": 8, "lsb": 8}, {"name": "ITD", "msb": 7, "lsb": 7}, {"name": "nAA", "msb": 6, "lsb": 6}, {"name": "CP15BEN", "msb": 5, "lsb": 5}, {"name": "SA0", "msb": 4, "lsb": 4}, {"name": "SA", "msb": 3, "lsb": 3}, {"name": "C", "msb": 2, "lsb": 2}, {"name": "A", "msb": 1, "lsb": 1}, {"name": "M", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SCTLR_EL3", "fullname": "System Control Register (EL3)", "enc": [3, 6, 1, 0, 0], "fieldsets": [{"fields": [{"name": "DSSBS", "msb": 44, "lsb": 44}, {"name": "ATA", "msb": 43, "lsb": 43}, {"name": "TCF", "msb": 41, "lsb": 40}, {"name": "ITFSB", "msb": 37, "lsb": 37}, {"name": "BT", "msb": 36, "lsb": 36}, {"name": "EnIA", "msb": 31, "lsb": 31}, {"name": "EnIB", "msb": 30, "lsb": 30}, {"name": "EnDA", "msb": 27, "lsb": 27}, {"name": "EE", "msb": 25, "lsb": 25}, {"name": "EIS", "msb": 22, "lsb": 22}, {"name": "IESB", "msb": 21, "lsb": 21}, {"name": "WXN", "msb": 19, "lsb": 19}, {"name": "EnDB", "msb": 13, "lsb": 13}, {"name": "I", "msb": 12, "lsb": 12}, {"name": "EOS", "msb": 11, "lsb": 11}, {"name": "nAA", "msb": 6, "lsb": 6}, {"name": "SA", "msb": 3, "lsb": 3}, {"name": "C", "msb": 2, "lsb": 2}, {"name": "A", "msb": 1, "lsb": 1}, {"name": "M", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SCXTNUM_EL0", "fullname": "EL0 Read/Write Software Context Number", "enc": [3, 3, 13, 0, 7], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "SCXTNUM_EL1", "fullname": "EL1 Read/Write Software Context Number", "enc": [3, 0, 13, 0, 7], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "SCXTNUM_EL12", "fullname": "EL1 Read/Write Software Context Number", "enc": [3, 5, 13, 0, 7], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "SCXTNUM_EL1", "fullname": "EL2 Read/Write Software Context Number", "enc": [3, 0, 13, 0, 7], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "SCXTNUM_EL2", "fullname": "EL2 Read/Write Software Context Number", "enc": [3, 4, 13, 0, 7], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "SCXTNUM_EL3", "fullname": "EL3 Read/Write Software Context Number", "enc": [3, 6, 13, 0, 7], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "SDER32_EL2", "fullname": "AArch32 Secure Debug Enable Register", "enc": [3, 4, 1, 3, 1], "fieldsets": [{"fields": [{"name": "SUNIDEN", "msb": 1, "lsb": 1}, {"name": "SUIDEN", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SDER32_EL3", "fullname": "AArch32 Secure Debug Enable Register", "enc": [3, 6, 1, 1, 1], "fieldsets": [{"fields": [{"name": "SUNIDEN", "msb": 1, "lsb": 1}, {"name": "SUIDEN", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SP_EL0", "fullname": "Stack Pointer (EL0)", "enc": [3, 0, 4, 1, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "SP_EL1", "fullname": "Stack Pointer (EL1)", "enc": [3, 4, 4, 1, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "SP_EL2", "fullname": "Stack Pointer (EL2)", "enc": [3, 6, 4, 1, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "SPSel", "fullname": "Stack Pointer Select", "enc": [3, 0, 4, 2, 0], "fieldsets": [{"fields": [{"name": "SP", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SPSR_abt", "fullname": "Saved Program Status Register (Abort mode)", "enc": [3, 4, 4, 3, 1], "fieldsets": [{"fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "Q", "msb": 27, "lsb": 27}, {"name": "IT", "msb": 26, "lsb": 25}, {"name": "J", "msb": 24, "lsb": 24}, {"name": "SSBS", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "DIT", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "GE", "msb": 19, "lsb": 16}, {"name": "IT[7:2]", "msb": 15, "lsb": 10}, {"name": "E", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "T", "msb": 5, "lsb": 5}, {"name": "M[4:0]", "msb": 4, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SPSR_EL1", "fullname": "Saved Program Status Register (EL1)", "enc": [3, 0, 4, 0, 0], "fieldsets": [{"instance": "exception taken from AArch32", "fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "Q", "msb": 27, "lsb": 27}, {"name": "IT", "msb": 26, "lsb": 25}, {"name": "DIT", "msb": 24, "lsb": 24}, {"name": "SSBS", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "SS", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "GE", "msb": 19, "lsb": 16}, {"name": "IT[7:2]", "msb": 15, "lsb": 10}, {"name": "E", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "T", "msb": 5, "lsb": 5}, {"name": "M[4]", "msb": 4, "lsb": 4}, {"name": "M[3:0]", "msb": 3, "lsb": 0}]}, {"instance": "exception taken from AArch64", "fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "TCO", "msb": 25, "lsb": 25}, {"name": "DIT", "msb": 24, "lsb": 24}, {"name": "UAO", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "SS", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "SSBS", "msb": 12, "lsb": 12}, {"name": "BTYPE", "msb": 11, "lsb": 10}, {"name": "D", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "M[4]", "msb": 4, "lsb": 4}, {"name": "M[3:0]", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SPSR_EL12", "fullname": "Saved Program Status Register (EL1)", "enc": [3, 5, 4, 0, 0], "fieldsets": [{"instance": "exception taken from AArch32", "fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "Q", "msb": 27, "lsb": 27}, {"name": "IT", "msb": 26, "lsb": 25}, {"name": "DIT", "msb": 24, "lsb": 24}, {"name": "SSBS", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "SS", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "GE", "msb": 19, "lsb": 16}, {"name": "IT[7:2]", "msb": 15, "lsb": 10}, {"name": "E", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "T", "msb": 5, "lsb": 5}, {"name": "M[4]", "msb": 4, "lsb": 4}, {"name": "M[3:0]", "msb": 3, "lsb": 0}]}, {"instance": "exception taken from AArch64", "fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "TCO", "msb": 25, "lsb": 25}, {"name": "DIT", "msb": 24, "lsb": 24}, {"name": "UAO", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "SS", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "SSBS", "msb": 12, "lsb": 12}, {"name": "BTYPE", "msb": 11, "lsb": 10}, {"name": "D", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "M[4]", "msb": 4, "lsb": 4}, {"name": "M[3:0]", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SPSR_EL2", "fullname": "Saved Program Status Register (EL1)", "enc": [3, 4, 4, 0, 0], "fieldsets": [{"instance": "exception taken from AArch32", "fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "Q", "msb": 27, "lsb": 27}, {"name": "IT", "msb": 26, "lsb": 25}, {"name": "DIT", "msb": 24, "lsb": 24}, {"name": "SSBS", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "SS", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "GE", "msb": 19, "lsb": 16}, {"name": "IT[7:2]", "msb": 15, "lsb": 10}, {"name": "E", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "T", "msb": 5, "lsb": 5}, {"name": "M[4]", "msb": 4, "lsb": 4}, {"name": "M[3:0]", "msb": 3, "lsb": 0}]}, {"instance": "exception taken from AArch64", "fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "TCO", "msb": 25, "lsb": 25}, {"name": "DIT", "msb": 24, "lsb": 24}, {"name": "UAO", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "SS", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "SSBS", "msb": 12, "lsb": 12}, {"name": "BTYPE", "msb": 11, "lsb": 10}, {"name": "D", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "M[4]", "msb": 4, "lsb": 4}, {"name": "M[3:0]", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SPSR_EL1", "fullname": "Saved Program Status Register (EL2)", "enc": [3, 0, 4, 0, 0], "fieldsets": [{"instance": "exception taken from AArch32", "fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "Q", "msb": 27, "lsb": 27}, {"name": "IT", "msb": 26, "lsb": 25}, {"name": "DIT", "msb": 24, "lsb": 24}, {"name": "SSBS", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "SS", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "GE", "msb": 19, "lsb": 16}, {"name": "IT[7:2]", "msb": 15, "lsb": 10}, {"name": "E", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "T", "msb": 5, "lsb": 5}, {"name": "M[4]", "msb": 4, "lsb": 4}, {"name": "M[3:0]", "msb": 3, "lsb": 0}]}, {"instance": "exception taken from AArch64", "fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "TCO", "msb": 25, "lsb": 25}, {"name": "DIT", "msb": 24, "lsb": 24}, {"name": "UAO", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "SS", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "SSBS", "msb": 12, "lsb": 12}, {"name": "BTYPE", "msb": 11, "lsb": 10}, {"name": "D", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "M[4]", "msb": 4, "lsb": 4}, {"name": "M[3:0]", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SPSR_EL2", "fullname": "Saved Program Status Register (EL2)", "enc": [3, 4, 4, 0, 0], "fieldsets": [{"instance": "exception taken from AArch32", "fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "Q", "msb": 27, "lsb": 27}, {"name": "IT", "msb": 26, "lsb": 25}, {"name": "DIT", "msb": 24, "lsb": 24}, {"name": "SSBS", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "SS", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "GE", "msb": 19, "lsb": 16}, {"name": "IT[7:2]", "msb": 15, "lsb": 10}, {"name": "E", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "T", "msb": 5, "lsb": 5}, {"name": "M[4]", "msb": 4, "lsb": 4}, {"name": "M[3:0]", "msb": 3, "lsb": 0}]}, {"instance": "exception taken from AArch64", "fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "TCO", "msb": 25, "lsb": 25}, {"name": "DIT", "msb": 24, "lsb": 24}, {"name": "UAO", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "SS", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "SSBS", "msb": 12, "lsb": 12}, {"name": "BTYPE", "msb": 11, "lsb": 10}, {"name": "D", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "M[4]", "msb": 4, "lsb": 4}, {"name": "M[3:0]", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SPSR_EL3", "fullname": "Saved Program Status Register (EL3)", "enc": [3, 6, 4, 0, 0], "fieldsets": [{"instance": "exception taken from AArch32", "fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "Q", "msb": 27, "lsb": 27}, {"name": "IT", "msb": 26, "lsb": 25}, {"name": "DIT", "msb": 24, "lsb": 24}, {"name": "SSBS", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "SS", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "GE", "msb": 19, "lsb": 16}, {"name": "IT[7:2]", "msb": 15, "lsb": 10}, {"name": "E", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "T", "msb": 5, "lsb": 5}, {"name": "M[4]", "msb": 4, "lsb": 4}, {"name": "M[3:0]", "msb": 3, "lsb": 0}]}, {"instance": "exception taken from AArch64", "fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "TCO", "msb": 25, "lsb": 25}, {"name": "DIT", "msb": 24, "lsb": 24}, {"name": "UAO", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "SS", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "SSBS", "msb": 12, "lsb": 12}, {"name": "BTYPE", "msb": 11, "lsb": 10}, {"name": "D", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "M[4]", "msb": 4, "lsb": 4}, {"name": "M[3:0]", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SPSR_fiq", "fullname": "Saved Program Status Register (FIQ mode)", "enc": [3, 4, 4, 3, 3], "fieldsets": [{"fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "Q", "msb": 27, "lsb": 27}, {"name": "IT", "msb": 26, "lsb": 25}, {"name": "J", "msb": 24, "lsb": 24}, {"name": "SSBS", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "DIT", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "GE", "msb": 19, "lsb": 16}, {"name": "IT[7:2]", "msb": 15, "lsb": 10}, {"name": "E", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "T", "msb": 5, "lsb": 5}, {"name": "M[4:0]", "msb": 4, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SPSR_irq", "fullname": "Saved Program Status Register (IRQ mode)", "enc": [3, 4, 4, 3, 0], "fieldsets": [{"fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "Q", "msb": 27, "lsb": 27}, {"name": "IT", "msb": 26, "lsb": 25}, {"name": "J", "msb": 24, "lsb": 24}, {"name": "SSBS", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "DIT", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "GE", "msb": 19, "lsb": 16}, {"name": "IT[7:2]", "msb": 15, "lsb": 10}, {"name": "E", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "T", "msb": 5, "lsb": 5}, {"name": "M[4:0]", "msb": 4, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SPSR_und", "fullname": "Saved Program Status Register (Undefined mode)", "enc": [3, 4, 4, 3, 2], "fieldsets": [{"fields": [{"name": "N", "msb": 31, "lsb": 31}, {"name": "Z", "msb": 30, "lsb": 30}, {"name": "C", "msb": 29, "lsb": 29}, {"name": "V", "msb": 28, "lsb": 28}, {"name": "Q", "msb": 27, "lsb": 27}, {"name": "IT", "msb": 26, "lsb": 25}, {"name": "J", "msb": 24, "lsb": 24}, {"name": "SSBS", "msb": 23, "lsb": 23}, {"name": "PAN", "msb": 22, "lsb": 22}, {"name": "DIT", "msb": 21, "lsb": 21}, {"name": "IL", "msb": 20, "lsb": 20}, {"name": "GE", "msb": 19, "lsb": 16}, {"name": "IT[7:2]", "msb": 15, "lsb": 10}, {"name": "E", "msb": 9, "lsb": 9}, {"name": "A", "msb": 8, "lsb": 8}, {"name": "I", "msb": 7, "lsb": 7}, {"name": "F", "msb": 6, "lsb": 6}, {"name": "T", "msb": 5, "lsb": 5}, {"name": "M[4:0]", "msb": 4, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "SSBS", "fullname": "Speculative Store Bypass Safe", "enc": [3, 3, 4, 2, 6], "fieldsets": [{"fields": [{"name": "SSBS", "msb": 12, "lsb": 12}]}], "width": 64}, {"index": 0, "name": "TCO", "fullname": "Tag Check Override", "enc": [3, 3, 4, 2, 7], "fieldsets": [{"fields": [{"name": "TCO", "msb": 25, "lsb": 25}]}], "width": 64}, {"index": 0, "name": "TCR_EL1", "fullname": "Translation Control Register (EL1)", "enc": [3, 0, 2, 0, 2], "fieldsets": [{"fields": [{"name": "DS", "msb": 59, "lsb": 59}, {"name": "TCMA1", "msb": 58, "lsb": 58}, {"name": "TCMA0", "msb": 57, "lsb": 57}, {"name": "E0PD1", "msb": 56, "lsb": 56}, {"name": "E0PD0", "msb": 55, "lsb": 55}, {"name": "NFD1", "msb": 54, "lsb": 54}, {"name": "NFD0", "msb": 53, "lsb": 53}, {"name": "TBID1", "msb": 52, "lsb": 52}, {"name": "TBID0", "msb": 51, "lsb": 51}, {"name": "HWU162", "msb": 50, "lsb": 50}, {"name": "HWU161", "msb": 49, "lsb": 49}, {"name": "HWU160", "msb": 48, "lsb": 48}, {"name": "HWU159", "msb": 47, "lsb": 47}, {"name": "HWU062", "msb": 46, "lsb": 46}, {"name": "HWU061", "msb": 45, "lsb": 45}, {"name": "HWU060", "msb": 44, "lsb": 44}, {"name": "HWU059", "msb": 43, "lsb": 43}, {"name": "HPD1", "msb": 42, "lsb": 42}, {"name": "HPD0", "msb": 41, "lsb": 41}, {"name": "HD", "msb": 40, "lsb": 40}, {"name": "HA", "msb": 39, "lsb": 39}, {"name": "TBI1", "msb": 38, "lsb": 38}, {"name": "TBI0", "msb": 37, "lsb": 37}, {"name": "AS", "msb": 36, "lsb": 36}, {"name": "IPS", "msb": 34, "lsb": 32}, {"name": "TG1", "msb": 31, "lsb": 30}, {"name": "SH1", "msb": 29, "lsb": 28}, {"name": "ORGN1", "msb": 27, "lsb": 26}, {"name": "IRGN1", "msb": 25, "lsb": 24}, {"name": "EPD1", "msb": 23, "lsb": 23}, {"name": "A1", "msb": 22, "lsb": 22}, {"name": "T1SZ", "msb": 21, "lsb": 16}, {"name": "TG0", "msb": 15, "lsb": 14}, {"name": "SH0", "msb": 13, "lsb": 12}, {"name": "ORGN0", "msb": 11, "lsb": 10}, {"name": "IRGN0", "msb": 9, "lsb": 8}, {"name": "EPD0", "msb": 7, "lsb": 7}, {"name": "T0SZ", "msb": 5, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TCR_EL12", "fullname": "Translation Control Register (EL1)", "enc": [3, 5, 2, 0, 2], "fieldsets": [{"fields": [{"name": "DS", "msb": 59, "lsb": 59}, {"name": "TCMA1", "msb": 58, "lsb": 58}, {"name": "TCMA0", "msb": 57, "lsb": 57}, {"name": "E0PD1", "msb": 56, "lsb": 56}, {"name": "E0PD0", "msb": 55, "lsb": 55}, {"name": "NFD1", "msb": 54, "lsb": 54}, {"name": "NFD0", "msb": 53, "lsb": 53}, {"name": "TBID1", "msb": 52, "lsb": 52}, {"name": "TBID0", "msb": 51, "lsb": 51}, {"name": "HWU162", "msb": 50, "lsb": 50}, {"name": "HWU161", "msb": 49, "lsb": 49}, {"name": "HWU160", "msb": 48, "lsb": 48}, {"name": "HWU159", "msb": 47, "lsb": 47}, {"name": "HWU062", "msb": 46, "lsb": 46}, {"name": "HWU061", "msb": 45, "lsb": 45}, {"name": "HWU060", "msb": 44, "lsb": 44}, {"name": "HWU059", "msb": 43, "lsb": 43}, {"name": "HPD1", "msb": 42, "lsb": 42}, {"name": "HPD0", "msb": 41, "lsb": 41}, {"name": "HD", "msb": 40, "lsb": 40}, {"name": "HA", "msb": 39, "lsb": 39}, {"name": "TBI1", "msb": 38, "lsb": 38}, {"name": "TBI0", "msb": 37, "lsb": 37}, {"name": "AS", "msb": 36, "lsb": 36}, {"name": "IPS", "msb": 34, "lsb": 32}, {"name": "TG1", "msb": 31, "lsb": 30}, {"name": "SH1", "msb": 29, "lsb": 28}, {"name": "ORGN1", "msb": 27, "lsb": 26}, {"name": "IRGN1", "msb": 25, "lsb": 24}, {"name": "EPD1", "msb": 23, "lsb": 23}, {"name": "A1", "msb": 22, "lsb": 22}, {"name": "T1SZ", "msb": 21, "lsb": 16}, {"name": "TG0", "msb": 15, "lsb": 14}, {"name": "SH0", "msb": 13, "lsb": 12}, {"name": "ORGN0", "msb": 11, "lsb": 10}, {"name": "IRGN0", "msb": 9, "lsb": 8}, {"name": "EPD0", "msb": 7, "lsb": 7}, {"name": "T0SZ", "msb": 5, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TCR_EL1", "fullname": "Translation Control Register (EL2)", "enc": [3, 0, 2, 0, 2], "fieldsets": [{"instance": "HCR_EL2.E2H==0", "fields": [{"name": "DS", "msb": 32, "lsb": 32}, {"name": "TCMA", "msb": 30, "lsb": 30}, {"name": "TBID", "msb": 29, "lsb": 29}, {"name": "HWU62", "msb": 28, "lsb": 28}, {"name": "HWU61", "msb": 27, "lsb": 27}, {"name": "HWU60", "msb": 26, "lsb": 26}, {"name": "HWU59", "msb": 25, "lsb": 25}, {"name": "HPD", "msb": 24, "lsb": 24}, {"name": "HD", "msb": 22, "lsb": 22}, {"name": "HA", "msb": 21, "lsb": 21}, {"name": "TBI", "msb": 20, "lsb": 20}, {"name": "PS", "msb": 18, "lsb": 16}, {"name": "TG0", "msb": 15, "lsb": 14}, {"name": "SH0", "msb": 13, "lsb": 12}, {"name": "ORGN0", "msb": 11, "lsb": 10}, {"name": "IRGN0", "msb": 9, "lsb": 8}, {"name": "T0SZ", "msb": 5, "lsb": 0}]}, {"instance": "HCR_EL2.E2H==1", "fields": [{"name": "DS", "msb": 59, "lsb": 59}, {"name": "TCMA1", "msb": 58, "lsb": 58}, {"name": "TCMA0", "msb": 57, "lsb": 57}, {"name": "E0PD1", "msb": 56, "lsb": 56}, {"name": "E0PD0", "msb": 55, "lsb": 55}, {"name": "NFD1", "msb": 54, "lsb": 54}, {"name": "NFD0", "msb": 53, "lsb": 53}, {"name": "TBID1", "msb": 52, "lsb": 52}, {"name": "TBID0", "msb": 51, "lsb": 51}, {"name": "HWU162", "msb": 50, "lsb": 50}, {"name": "HWU161", "msb": 49, "lsb": 49}, {"name": "HWU160", "msb": 48, "lsb": 48}, {"name": "HWU159", "msb": 47, "lsb": 47}, {"name": "HWU062", "msb": 46, "lsb": 46}, {"name": "HWU061", "msb": 45, "lsb": 45}, {"name": "HWU060", "msb": 44, "lsb": 44}, {"name": "HWU059", "msb": 43, "lsb": 43}, {"name": "HPD1", "msb": 42, "lsb": 42}, {"name": "HPD0", "msb": 41, "lsb": 41}, {"name": "HD", "msb": 40, "lsb": 40}, {"name": "HA", "msb": 39, "lsb": 39}, {"name": "TBI1", "msb": 38, "lsb": 38}, {"name": "TBI0", "msb": 37, "lsb": 37}, {"name": "AS", "msb": 36, "lsb": 36}, {"name": "IPS", "msb": 34, "lsb": 32}, {"name": "TG1", "msb": 31, "lsb": 30}, {"name": "SH1", "msb": 29, "lsb": 28}, {"name": "ORGN1", "msb": 27, "lsb": 26}, {"name": "IRGN1", "msb": 25, "lsb": 24}, {"name": "EPD1", "msb": 23, "lsb": 23}, {"name": "A1", "msb": 22, "lsb": 22}, {"name": "T1SZ", "msb": 21, "lsb": 16}, {"name": "TG0", "msb": 15, "lsb": 14}, {"name": "SH0", "msb": 13, "lsb": 12}, {"name": "ORGN0", "msb": 11, "lsb": 10}, {"name": "IRGN0", "msb": 9, "lsb": 8}, {"name": "EPD0", "msb": 7, "lsb": 7}, {"name": "T0SZ", "msb": 5, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TCR_EL2", "fullname": "Translation Control Register (EL2)", "enc": [3, 4, 2, 0, 2], "fieldsets": [{"instance": "HCR_EL2.E2H==0", "fields": [{"name": "DS", "msb": 32, "lsb": 32}, {"name": "TCMA", "msb": 30, "lsb": 30}, {"name": "TBID", "msb": 29, "lsb": 29}, {"name": "HWU62", "msb": 28, "lsb": 28}, {"name": "HWU61", "msb": 27, "lsb": 27}, {"name": "HWU60", "msb": 26, "lsb": 26}, {"name": "HWU59", "msb": 25, "lsb": 25}, {"name": "HPD", "msb": 24, "lsb": 24}, {"name": "HD", "msb": 22, "lsb": 22}, {"name": "HA", "msb": 21, "lsb": 21}, {"name": "TBI", "msb": 20, "lsb": 20}, {"name": "PS", "msb": 18, "lsb": 16}, {"name": "TG0", "msb": 15, "lsb": 14}, {"name": "SH0", "msb": 13, "lsb": 12}, {"name": "ORGN0", "msb": 11, "lsb": 10}, {"name": "IRGN0", "msb": 9, "lsb": 8}, {"name": "T0SZ", "msb": 5, "lsb": 0}]}, {"instance": "HCR_EL2.E2H==1", "fields": [{"name": "DS", "msb": 59, "lsb": 59}, {"name": "TCMA1", "msb": 58, "lsb": 58}, {"name": "TCMA0", "msb": 57, "lsb": 57}, {"name": "E0PD1", "msb": 56, "lsb": 56}, {"name": "E0PD0", "msb": 55, "lsb": 55}, {"name": "NFD1", "msb": 54, "lsb": 54}, {"name": "NFD0", "msb": 53, "lsb": 53}, {"name": "TBID1", "msb": 52, "lsb": 52}, {"name": "TBID0", "msb": 51, "lsb": 51}, {"name": "HWU162", "msb": 50, "lsb": 50}, {"name": "HWU161", "msb": 49, "lsb": 49}, {"name": "HWU160", "msb": 48, "lsb": 48}, {"name": "HWU159", "msb": 47, "lsb": 47}, {"name": "HWU062", "msb": 46, "lsb": 46}, {"name": "HWU061", "msb": 45, "lsb": 45}, {"name": "HWU060", "msb": 44, "lsb": 44}, {"name": "HWU059", "msb": 43, "lsb": 43}, {"name": "HPD1", "msb": 42, "lsb": 42}, {"name": "HPD0", "msb": 41, "lsb": 41}, {"name": "HD", "msb": 40, "lsb": 40}, {"name": "HA", "msb": 39, "lsb": 39}, {"name": "TBI1", "msb": 38, "lsb": 38}, {"name": "TBI0", "msb": 37, "lsb": 37}, {"name": "AS", "msb": 36, "lsb": 36}, {"name": "IPS", "msb": 34, "lsb": 32}, {"name": "TG1", "msb": 31, "lsb": 30}, {"name": "SH1", "msb": 29, "lsb": 28}, {"name": "ORGN1", "msb": 27, "lsb": 26}, {"name": "IRGN1", "msb": 25, "lsb": 24}, {"name": "EPD1", "msb": 23, "lsb": 23}, {"name": "A1", "msb": 22, "lsb": 22}, {"name": "T1SZ", "msb": 21, "lsb": 16}, {"name": "TG0", "msb": 15, "lsb": 14}, {"name": "SH0", "msb": 13, "lsb": 12}, {"name": "ORGN0", "msb": 11, "lsb": 10}, {"name": "IRGN0", "msb": 9, "lsb": 8}, {"name": "EPD0", "msb": 7, "lsb": 7}, {"name": "T0SZ", "msb": 5, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TCR_EL3", "fullname": "Translation Control Register (EL3)", "enc": [3, 6, 2, 0, 2], "fieldsets": [{"fields": [{"name": "DS", "msb": 32, "lsb": 32}, {"name": "TCMA", "msb": 30, "lsb": 30}, {"name": "TBID", "msb": 29, "lsb": 29}, {"name": "HWU62", "msb": 28, "lsb": 28}, {"name": "HWU61", "msb": 27, "lsb": 27}, {"name": "HWU60", "msb": 26, "lsb": 26}, {"name": "HWU59", "msb": 25, "lsb": 25}, {"name": "HPD", "msb": 24, "lsb": 24}, {"name": "HD", "msb": 22, "lsb": 22}, {"name": "HA", "msb": 21, "lsb": 21}, {"name": "TBI", "msb": 20, "lsb": 20}, {"name": "PS", "msb": 18, "lsb": 16}, {"name": "TG0", "msb": 15, "lsb": 14}, {"name": "SH0", "msb": 13, "lsb": 12}, {"name": "ORGN0", "msb": 11, "lsb": 10}, {"name": "IRGN0", "msb": 9, "lsb": 8}, {"name": "T0SZ", "msb": 5, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TFSRE0_EL1", "fullname": "Tag Fault Status Register (EL0).", "enc": [3, 0, 5, 6, 1], "fieldsets": [{"fields": [{"name": "TF1", "msb": 1, "lsb": 1}, {"name": "TF0", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TFSR_EL1", "fullname": "Tag Fault Status Register (EL1)", "enc": [3, 0, 5, 6, 0], "fieldsets": [{"fields": [{"name": "TF1", "msb": 1, "lsb": 1}, {"name": "TF0", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TFSR_EL12", "fullname": "Tag Fault Status Register (EL1)", "enc": [3, 5, 5, 6, 0], "fieldsets": [{"fields": [{"name": "TF1", "msb": 1, "lsb": 1}, {"name": "TF0", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TFSR_EL2", "fullname": "Tag Fault Status Register (EL1)", "enc": [3, 4, 5, 6, 0], "fieldsets": [{"fields": [{"name": "TF1", "msb": 1, "lsb": 1}, {"name": "TF0", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TFSR_EL1", "fullname": "Tag Fault Status Register (EL2)", "enc": [3, 0, 5, 6, 0], "fieldsets": [{"fields": [{"name": "TF1", "msb": 1, "lsb": 1}, {"name": "TF0", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TFSR_EL2", "fullname": "Tag Fault Status Register (EL2)", "enc": [3, 4, 5, 6, 0], "fieldsets": [{"fields": [{"name": "TF1", "msb": 1, "lsb": 1}, {"name": "TF0", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TFSR_EL3", "fullname": "Tag Fault Status Register (EL3)", "enc": [3, 6, 5, 6, 0], "fieldsets": [{"fields": [{"name": "TF0", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TPIDR_EL0", "fullname": "EL0 Read/Write Software Thread ID Register", "enc": [3, 3, 13, 0, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "TPIDR_EL1", "fullname": "EL1 Software Thread ID Register", "enc": [3, 0, 13, 0, 4], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "TPIDR_EL2", "fullname": "EL2 Software Thread ID Register", "enc": [3, 4, 13, 0, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "TPIDR_EL3", "fullname": "EL3 Software Thread ID Register", "enc": [3, 6, 13, 0, 2], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "TPIDRRO_EL0", "fullname": "EL0 Read-Only Software Thread ID Register", "enc": [3, 3, 13, 0, 3], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "TRFCR_EL1", "fullname": "Trace Filter Control Register (EL1)", "enc": [3, 0, 1, 2, 1], "fieldsets": [{"fields": [{"name": "TS", "msb": 6, "lsb": 5}, {"name": "E1TRE", "msb": 1, "lsb": 1}, {"name": "E0TRE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TRFCR_EL12", "fullname": "Trace Filter Control Register (EL1)", "enc": [3, 5, 1, 2, 1], "fieldsets": [{"fields": [{"name": "TS", "msb": 6, "lsb": 5}, {"name": "E1TRE", "msb": 1, "lsb": 1}, {"name": "E0TRE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TRFCR_EL1", "fullname": "Trace Filter Control Register (EL2)", "enc": [3, 0, 1, 2, 1], "fieldsets": [{"fields": [{"name": "TS", "msb": 6, "lsb": 5}, {"name": "CX", "msb": 3, "lsb": 3}, {"name": "E2TRE", "msb": 1, "lsb": 1}, {"name": "E0HTRE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TRFCR_EL2", "fullname": "Trace Filter Control Register (EL2)", "enc": [3, 4, 1, 2, 1], "fieldsets": [{"fields": [{"name": "TS", "msb": 6, "lsb": 5}, {"name": "CX", "msb": 3, "lsb": 3}, {"name": "E2TRE", "msb": 1, "lsb": 1}, {"name": "E0HTRE", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TTBR0_EL1", "fullname": "Translation Table Base Register 0 (EL1)", "enc": [3, 0, 2, 0, 0], "fieldsets": [{"fields": [{"name": "ASID", "msb": 63, "lsb": 48}, {"name": "BADDR[47:1]", "msb": 47, "lsb": 1}, {"name": "CnP", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TTBR0_EL12", "fullname": "Translation Table Base Register 0 (EL1)", "enc": [3, 5, 2, 0, 0], "fieldsets": [{"fields": [{"name": "ASID", "msb": 63, "lsb": 48}, {"name": "BADDR[47:1]", "msb": 47, "lsb": 1}, {"name": "CnP", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TTBR0_EL1", "fullname": "Translation Table Base Register 0 (EL2)", "enc": [3, 0, 2, 0, 0], "fieldsets": [{"fields": [{"name": "ASID", "msb": 63, "lsb": 48}, {"name": "BADDR[47:1]", "msb": 47, "lsb": 1}, {"name": "CnP", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TTBR0_EL2", "fullname": "Translation Table Base Register 0 (EL2)", "enc": [3, 4, 2, 0, 0], "fieldsets": [{"fields": [{"name": "ASID", "msb": 63, "lsb": 48}, {"name": "BADDR[47:1]", "msb": 47, "lsb": 1}, {"name": "CnP", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TTBR0_EL3", "fullname": "Translation Table Base Register 0 (EL3)", "enc": [3, 6, 2, 0, 0], "fieldsets": [{"fields": [{"name": "BADDR[47:1]", "msb": 47, "lsb": 1}, {"name": "CnP", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TTBR1_EL1", "fullname": "Translation Table Base Register 1 (EL1)", "enc": [3, 0, 2, 0, 1], "fieldsets": [{"fields": [{"name": "ASID", "msb": 63, "lsb": 48}, {"name": "BADDR[47:1]", "msb": 47, "lsb": 1}, {"name": "CnP", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TTBR1_EL12", "fullname": "Translation Table Base Register 1 (EL1)", "enc": [3, 5, 2, 0, 1], "fieldsets": [{"fields": [{"name": "ASID", "msb": 63, "lsb": 48}, {"name": "BADDR[47:1]", "msb": 47, "lsb": 1}, {"name": "CnP", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TTBR1_EL1", "fullname": "Translation Table Base Register 1 (EL2)", "enc": [3, 0, 2, 0, 1], "fieldsets": [{"fields": [{"name": "ASID", "msb": 63, "lsb": 48}, {"name": "BADDR[47:1]", "msb": 47, "lsb": 1}, {"name": "CnP", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "TTBR1_EL2", "fullname": "Translation Table Base Register 1 (EL2)", "enc": [3, 4, 2, 0, 1], "fieldsets": [{"fields": [{"name": "ASID", "msb": 63, "lsb": 48}, {"name": "BADDR[47:1]", "msb": 47, "lsb": 1}, {"name": "CnP", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "UAO", "fullname": "User Access Override", "enc": [3, 0, 4, 2, 4], "fieldsets": [{"fields": [{"name": "UAO", "msb": 23, "lsb": 23}]}], "width": 64}, {"index": 0, "name": "VBAR_EL1", "fullname": "Vector Base Address Register (EL1)", "enc": [3, 0, 12, 0, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "VBAR_EL12", "fullname": "Vector Base Address Register (EL1)", "enc": [3, 5, 12, 0, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "VBAR_EL1", "fullname": "Vector Base Address Register (EL2)", "enc": [3, 0, 12, 0, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "VBAR_EL2", "fullname": "Vector Base Address Register (EL2)", "enc": [3, 4, 12, 0, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "VBAR_EL3", "fullname": "Vector Base Address Register (EL3)", "enc": [3, 6, 12, 0, 0], "fieldsets": [{"fields": []}], "width": 64}, {"index": 0, "name": "DISR_EL1", "fullname": "Virtual Deferred Interrupt Status Register", "enc": [3, 0, 12, 1, 1], "fieldsets": [{"fields": [{"name": "A", "msb": 31, "lsb": 31}, {"name": "IDS", "msb": 24, "lsb": 24}, {"name": "ISS", "msb": 23, "lsb": 0}]}, {"fields": [{"name": "A", "msb": 31, "lsb": 31}, {"name": "AET", "msb": 15, "lsb": 14}, {"name": "ExT", "msb": 12, "lsb": 12}, {"name": "FS", "msb": 10, "lsb": 10}, {"name": "LPAE", "msb": 9, "lsb": 9}, {"name": "FS[3:0]", "msb": 3, "lsb": 0}]}, {"fields": [{"name": "A", "msb": 31, "lsb": 31}, {"name": "AET", "msb": 15, "lsb": 14}, {"name": "ExT", "msb": 12, "lsb": 12}, {"name": "LPAE", "msb": 9, "lsb": 9}, {"name": "STATUS", "msb": 5, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "VDISR_EL2", "fullname": "Virtual Deferred Interrupt Status Register", "enc": [3, 4, 12, 1, 1], "fieldsets": [{"fields": [{"name": "A", "msb": 31, "lsb": 31}, {"name": "IDS", "msb": 24, "lsb": 24}, {"name": "ISS", "msb": 23, "lsb": 0}]}, {"fields": [{"name": "A", "msb": 31, "lsb": 31}, {"name": "AET", "msb": 15, "lsb": 14}, {"name": "ExT", "msb": 12, "lsb": 12}, {"name": "FS", "msb": 10, "lsb": 10}, {"name": "LPAE", "msb": 9, "lsb": 9}, {"name": "FS[3:0]", "msb": 3, "lsb": 0}]}, {"fields": [{"name": "A", "msb": 31, "lsb": 31}, {"name": "AET", "msb": 15, "lsb": 14}, {"name": "ExT", "msb": 12, "lsb": 12}, {"name": "LPAE", "msb": 9, "lsb": 9}, {"name": "STATUS", "msb": 5, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "MPIDR_EL1", "fullname": "Virtualization Multiprocessor ID Register", "enc": [3, 0, 0, 0, 5], "fieldsets": [{"fields": [{"name": "Aff3", "msb": 39, "lsb": 32}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "MT", "msb": 24, "lsb": 24}, {"name": "Aff2", "msb": 23, "lsb": 16}, {"name": "Aff1", "msb": 15, "lsb": 8}, {"name": "Aff0", "msb": 7, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "VMPIDR_EL2", "fullname": "Virtualization Multiprocessor ID Register", "enc": [3, 4, 0, 0, 5], "fieldsets": [{"fields": [{"name": "Aff3", "msb": 39, "lsb": 32}, {"name": "U", "msb": 30, "lsb": 30}, {"name": "MT", "msb": 24, "lsb": 24}, {"name": "Aff2", "msb": 23, "lsb": 16}, {"name": "Aff1", "msb": 15, "lsb": 8}, {"name": "Aff0", "msb": 7, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "VNCR_EL2", "fullname": "Virtual Nested Control Register", "enc": [3, 4, 2, 2, 0], "fieldsets": [{"fields": [{"name": "RESS", "msb": 63, "lsb": 53}, {"name": "BADDR", "msb": 52, "lsb": 12}]}], "width": 64}, {"index": 0, "name": "MIDR_EL1", "fullname": "Virtualization Processor ID Register", "enc": [3, 0, 0, 0, 0], "fieldsets": [{"fields": [{"name": "Implementer", "msb": 31, "lsb": 24}, {"name": "Variant", "msb": 23, "lsb": 20}, {"name": "Architecture", "msb": 19, "lsb": 16}, {"name": "PartNum", "msb": 15, "lsb": 4}, {"name": "Revision", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "VPIDR_EL2", "fullname": "Virtualization Processor ID Register", "enc": [3, 4, 0, 0, 0], "fieldsets": [{"fields": [{"name": "Implementer", "msb": 31, "lsb": 24}, {"name": "Variant", "msb": 23, "lsb": 20}, {"name": "Architecture", "msb": 19, "lsb": 16}, {"name": "PartNum", "msb": 15, "lsb": 4}, {"name": "Revision", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "VSESR_EL2", "fullname": "Virtual SError Exception Syndrome Register", "enc": [3, 4, 5, 2, 3], "fieldsets": [{"fields": [{"name": "AET", "msb": 15, "lsb": 14}, {"name": "ExT", "msb": 12, "lsb": 12}]}, {"fields": [{"name": "IDS", "msb": 24, "lsb": 24}, {"name": "ISS", "msb": 23, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "VSTCR_EL2", "fullname": "Virtualization Secure Translation Control Register", "enc": [3, 4, 2, 6, 2], "fieldsets": [{"instance": "Profile(A)", "fields": [{"name": "SL2", "msb": 33, "lsb": 33}, {"name": "SA", "msb": 30, "lsb": 30}, {"name": "SW", "msb": 29, "lsb": 29}, {"name": "TG0", "msb": 15, "lsb": 14}, {"name": "SL0", "msb": 7, "lsb": 6}, {"name": "SL0", "msb": 7, "lsb": 6}, {"name": "T0SZ", "msb": 5, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "VSTTBR_EL2", "fullname": "Virtualization Secure Translation Table Base Register", "enc": [3, 4, 2, 6, 0], "fieldsets": [{"fields": [{"name": "BADDR", "msb": 47, "lsb": 1}, {"name": "CnP", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "VTCR_EL2", "fullname": "Virtualization Translation Control Register", "enc": [3, 4, 2, 1, 2], "fieldsets": [{"instance": "Profile(A)", "fields": [{"name": "SL2", "msb": 33, "lsb": 33}, {"name": "DS", "msb": 32, "lsb": 32}, {"name": "NSA", "msb": 30, "lsb": 30}, {"name": "NSW", "msb": 29, "lsb": 29}, {"name": "HWU62", "msb": 28, "lsb": 28}, {"name": "HWU61", "msb": 27, "lsb": 27}, {"name": "HWU60", "msb": 26, "lsb": 26}, {"name": "HWU59", "msb": 25, "lsb": 25}, {"name": "HD", "msb": 22, "lsb": 22}, {"name": "HA", "msb": 21, "lsb": 21}, {"name": "VS", "msb": 19, "lsb": 19}, {"name": "PS", "msb": 18, "lsb": 16}, {"name": "TG0", "msb": 15, "lsb": 14}, {"name": "SH0", "msb": 13, "lsb": 12}, {"name": "ORGN0", "msb": 11, "lsb": 10}, {"name": "IRGN0", "msb": 9, "lsb": 8}, {"name": "SL0", "msb": 7, "lsb": 6}, {"name": "SL0", "msb": 7, "lsb": 6}, {"name": "T0SZ", "msb": 5, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "VTTBR_EL2", "fullname": "Virtualization Translation Table Base Register", "enc": [3, 4, 2, 1, 0], "fieldsets": [{"fields": [{"name": "VMID", "msb": 63, "lsb": 48}, {"name": "BADDR", "msb": 47, "lsb": 1}, {"name": "CnP", "msb": 0, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ZCR_EL1", "fullname": "SVE Control Register (EL1)", "enc": [3, 0, 1, 2, 0], "fieldsets": [{"fields": [{"name": "LEN", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ZCR_EL12", "fullname": "SVE Control Register (EL1)", "enc": [3, 5, 1, 2, 0], "fieldsets": [{"fields": [{"name": "LEN", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ZCR_EL1", "fullname": "SVE Control Register (EL2)", "enc": [3, 0, 1, 2, 0], "fieldsets": [{"fields": [{"name": "LEN", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ZCR_EL2", "fullname": "SVE Control Register (EL2)", "enc": [3, 4, 1, 2, 0], "fieldsets": [{"fields": [{"name": "LEN", "msb": 3, "lsb": 0}]}], "width": 64}, {"index": 0, "name": "ZCR_EL3", "fullname": "SVE Control Register (EL3)", "enc": [3, 6, 1, 2, 0], "fieldsets": [{"fields": [{"name": "LEN", "msb": 3, "lsb": 0}]}], "width": 64}] |