mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-26 08:20:18 +00:00
442 lines
13 KiB
C
442 lines
13 KiB
C
/* SPDX-License-Identifier: MIT */
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#ifndef UTILS_H
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#define UTILS_H
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#include "types.h"
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#define printf(...) debug_printf(__VA_ARGS__)
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#ifdef DEBUG
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#define dprintf(...) debug_printf(__VA_ARGS__)
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#else
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#define dprintf(...) \
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do { \
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} while (0)
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#endif
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#define BIT(x) (1UL << (x))
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#define MASK(x) (BIT(x) - 1)
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#define GENMASK(msb, lsb) ((BIT((msb + 1) - (lsb)) - 1) << (lsb))
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#define _FIELD_LSB(field) ((field) & ~(field - 1))
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#define FIELD_PREP(field, val) ((val) * (_FIELD_LSB(field)))
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#define FIELD_GET(field, val) (((val) & (field)) / _FIELD_LSB(field))
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#define ALIGN_UP(x, a) (((x) + ((a)-1)) & ~((a)-1))
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#define ALIGN_DOWN(x, a) ((x) & ~((a)-1))
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#define min(a, b) (((a) < (b)) ? (a) : (b))
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#define max(a, b) (((a) > (b)) ? (a) : (b))
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#define USEC_PER_SEC 1000000L
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static inline u64 read64(u64 addr)
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{
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u64 data;
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__asm__ volatile("ldr\t%0, [%1]" : "=r"(data) : "r"(addr) : "memory");
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return data;
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}
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static inline void write64(u64 addr, u64 data)
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{
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__asm__ volatile("str\t%0, [%1]" : : "r"(data), "r"(addr) : "memory");
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}
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static inline u64 set64(u64 addr, u64 set)
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{
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u64 data;
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__asm__ volatile("ldr\t%0, [%1]\n"
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"\torr\t%0, %0, %2\n"
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"\tstr\t%0, [%1]"
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: "=&r"(data)
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: "r"(addr), "r"(set)
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: "memory");
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return data;
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}
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static inline u64 clear64(u64 addr, u64 clear)
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{
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u64 data;
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__asm__ volatile("ldr\t%0, [%1]\n"
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"\tbic\t%0, %0, %2\n"
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"\tstr\t%0, [%1]"
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: "=&r"(data)
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: "r"(addr), "r"(clear)
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: "memory");
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return data;
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}
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static inline u64 mask64(u64 addr, u64 clear, u64 set)
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{
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u64 data;
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__asm__ volatile("ldr\t%0, [%1]\n"
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"\tbic\t%0, %0, %3\n"
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"\torr\t%0, %0, %2\n"
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"\tstr\t%0, [%1]"
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: "=&r"(data)
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: "r"(addr), "r"(set), "r"(clear)
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: "memory");
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return data;
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}
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static inline u64 writeread64(u64 addr, u64 data)
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{
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write64(addr, data);
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return read64(addr);
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}
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static inline u32 read32(u64 addr)
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{
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u32 data;
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__asm__ volatile("ldr\t%w0, [%1]" : "=r"(data) : "r"(addr) : "memory");
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return data;
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}
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static inline void write32(u64 addr, u32 data)
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{
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__asm__ volatile("str\t%w0, [%1]" : : "r"(data), "r"(addr) : "memory");
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}
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static inline u32 writeread32(u64 addr, u32 data)
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{
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write32(addr, data);
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return read32(addr);
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}
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static inline u32 set32(u64 addr, u32 set)
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{
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u32 data;
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__asm__ volatile("ldr\t%w0, [%1]\n"
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"\torr\t%w0, %w0, %w2\n"
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"\tstr\t%w0, [%1]"
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: "=&r"(data)
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: "r"(addr), "r"(set)
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: "memory");
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return data;
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}
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static inline u32 clear32(u64 addr, u32 clear)
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{
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u32 data;
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__asm__ volatile("ldr\t%w0, [%1]\n"
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"\tbic\t%w0, %w0, %w2\n"
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"\tstr\t%w0, [%1]"
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: "=&r"(data)
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: "r"(addr), "r"(clear)
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: "memory");
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return data;
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}
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static inline u32 mask32(u64 addr, u32 clear, u32 set)
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{
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u32 data;
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__asm__ volatile("ldr\t%w0, [%1]\n"
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"\tbic\t%w0, %w0, %w3\n"
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"\torr\t%w0, %w0, %w2\n"
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"\tstr\t%w0, [%1]"
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: "=&r"(data)
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: "r"(addr), "r"(set), "r"(clear)
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: "memory");
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return data;
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}
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static inline u16 read16(u64 addr)
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{
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u32 data;
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__asm__ volatile("ldrh\t%w0, [%1]" : "=r"(data) : "r"(addr) : "memory");
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return data;
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}
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static inline void write16(u64 addr, u16 data)
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{
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__asm__ volatile("strh\t%w0, [%1]" : : "r"(data), "r"(addr) : "memory");
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}
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static inline u16 set16(u64 addr, u16 set)
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{
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u16 data;
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__asm__ volatile("ldrh\t%w0, [%1]\n"
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"\torr\t%w0, %w0, %w2\n"
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"\tstrh\t%w0, [%1]"
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: "=&r"(data)
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: "r"(addr), "r"(set)
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: "memory"
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);
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return data;
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}
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static inline u16 clear16(u64 addr, u16 clear)
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{
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u16 data;
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__asm__ volatile("ldrh\t%w0, [%1]\n"
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"\tbic\t%w0, %w0, %w2\n"
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"\tstrh\t%w0, [%1]"
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: "=&r"(data)
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: "r"(addr), "r"(clear)
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: "memory");
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return data;
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}
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static inline u16 mask16(u64 addr, u16 clear, u16 set)
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{
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u16 data;
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__asm__ volatile("ldrh\t%w0, [%1]\n"
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"\tbic\t%w0, %w0, %w3\n"
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"\torr\t%w0, %w0, %w2\n"
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"\tstrh\t%w0, [%1]"
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: "=&r"(data)
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: "r"(addr), "r"(set), "r"(clear)
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: "memory");
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return data;
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}
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static inline u16 writeread16(u64 addr, u16 data)
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{
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write16(addr, data);
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return read16(addr);
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}
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static inline u8 read8(u64 addr)
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{
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u32 data;
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__asm__ volatile("ldrb\t%w0, [%1]" : "=r"(data) : "r"(addr) : "memory");
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return data;
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}
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static inline void write8(u64 addr, u8 data)
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{
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__asm__ volatile("strb\t%w0, [%1]" : : "r"(data), "r"(addr) : "memory");
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}
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static inline u8 set8(u64 addr, u8 set)
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{
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u8 data;
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__asm__ volatile("ldrb\t%w0, [%1]\n"
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"\torr\t%w0, %w0, %w2\n"
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"\tstrb\t%w0, [%1]"
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: "=&r"(data)
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: "r"(addr), "r"(set)
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: "memory");
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return data;
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}
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static inline u8 clear8(u64 addr, u8 clear)
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{
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u8 data;
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__asm__ volatile("ldrb\t%w0, [%1]\n"
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"\tbic\t%w0, %w0, %w2\n"
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"\tstrb\t%w0, [%1]"
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: "=&r"(data)
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: "r"(addr), "r"(clear)
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: "memory");
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return data;
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}
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static inline u8 mask8(u64 addr, u8 clear, u8 set)
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{
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u8 data;
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__asm__ volatile("ldrb\t%w0, [%1]\n"
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"\tbic\t%w0, %w0, %w3\n"
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"\torr\t%w0, %w0, %w2\n"
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"\tstrb\t%w0, [%1]"
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: "=&r"(data)
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: "r"(addr), "r"(set), "r"(clear)
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: "memory");
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return data;
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}
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static inline u8 writeread8(u64 addr, u8 data)
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{
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write8(addr, data);
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return read8(addr);
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}
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static inline void write64_lo_hi(u64 addr, u64 val)
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{
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write32(addr, val);
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write32(addr + 4, val >> 32);
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}
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#define _concat(a, _1, b, ...) a##b
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#define _sr_tkn_S(_0, _1, op0, op1, CRn, CRm, op2) s##op0##_##op1##_c##CRn##_c##CRm##_##op2
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#define _sr_tkn(a) a
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#define sr_tkn(...) _concat(_sr_tkn, __VA_ARGS__, )(__VA_ARGS__)
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#define __mrs(reg) \
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({ \
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u64 val; \
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__asm__ volatile("mrs\t%0, " #reg : "=r"(val)); \
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val; \
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})
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#define _mrs(reg) __mrs(reg)
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#define __msr(reg, val) \
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({ \
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u64 __val = (u64)val; \
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__asm__ volatile("msr\t" #reg ", %0" : : "r"(__val)); \
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})
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#define _msr(reg, val) __msr(reg, val)
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#define mrs(reg) _mrs(sr_tkn(reg))
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#define msr(reg, val) _msr(sr_tkn(reg), val)
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#define msr_sync(reg, val) \
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({ \
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_msr(sr_tkn(reg), val); \
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sysop("isb"); \
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})
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#define reg_clr(reg, bits) _msr(sr_tkn(reg), _mrs(sr_tkn(reg)) & ~(bits))
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#define reg_set(reg, bits) _msr(sr_tkn(reg), _mrs(sr_tkn(reg)) | bits)
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#define reg_mask(reg, clr, set) _msr(sr_tkn(reg), (_mrs(sr_tkn(reg)) & ~(clr)) | set)
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#define reg_clr_sync(reg, bits) \
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({ \
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reg_clr(sr_tkn(reg), bits); \
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sysop("isb"); \
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})
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#define reg_set_sync(reg, bits) \
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({ \
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reg_set(sr_tkn(reg), bits); \
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sysop("isb"); \
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})
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#define reg_mask_sync(reg, clr, set) \
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({ \
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reg_mask(sr_tkn(reg), clr, set); \
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sysop("isb"); \
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})
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#define sysop(op) __asm__ volatile(op ::: "memory")
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#define cacheop(op, val) ({ __asm__ volatile(op ", %0" : : "r"(val) : "memory"); })
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#define ic_ialluis() sysop("ic ialluis")
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#define ic_iallu() sysop("ic iallu")
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#define ic_iavau(p) cacheop("ic ivau", p)
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#define dc_ivac(p) cacheop("dc ivac", p)
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#define dc_isw(p) cacheop("dc isw", p)
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#define dc_csw(p) cacheop("dc csw", p)
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#define dc_cisw(p) cacheop("dc cisw", p)
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#define dc_zva(p) cacheop("dc zva", p)
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#define dc_cvac(p) cacheop("dc cvac", p)
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#define dc_cvau(p) cacheop("dc cvau", p)
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#define dc_civac(p) cacheop("dc civac", p)
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#define dma_mb() sysop("dmb osh")
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#define dma_rmb() sysop("dmb oshld")
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#define dma_wmb() sysop("dmb oshst")
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static inline int is_ecore(void)
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{
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return !(mrs(MPIDR_EL1) & (1 << 16));
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}
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static inline int in_el2(void)
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{
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return (mrs(CurrentEL) >> 2) == 2;
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}
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static inline int is_primary_core(void)
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{
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return mrs(MPIDR_EL1) == 0x80000000;
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}
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extern char _base[];
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extern char _rodata_end[];
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extern char _end[];
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extern char _payload_start[];
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extern char _payload_end[];
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/*
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* These functions are guaranteed to copy by reading from src and writing to dst
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* in <n>-bit units If size is not aligned, the remaining bytes are not copied
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*/
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void memcpy128(void *dst, void *src, size_t size);
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void memset64(void *dst, u64 value, size_t size);
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void memcpy64(void *dst, void *src, size_t size);
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void memset32(void *dst, u32 value, size_t size);
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void memcpy32(void *dst, void *src, size_t size);
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void memset16(void *dst, u16 value, size_t size);
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void memcpy16(void *dst, void *src, size_t size);
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void memset8(void *dst, u8 value, size_t size);
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void memcpy8(void *dst, void *src, size_t size);
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void get_simd_state(void *state);
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void put_simd_state(void *state);
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void hexdump(const void *d, size_t len);
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void regdump(u64 addr, size_t len);
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int snprintf(char *str, size_t size, const char *fmt, ...);
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int debug_printf(const char *fmt, ...) __attribute__((format(printf, 1, 2)));
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void udelay(u32 d);
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static inline u64 get_ticks(void)
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{
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return mrs(CNTPCT_EL0);
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}
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u64 ticks_to_msecs(u64 ticks);
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u64 ticks_to_usecs(u64 ticks);
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void reboot(void) __attribute__((noreturn));
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void flush_and_reboot(void) __attribute__((noreturn));
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u64 timeout_calculate(u32 usec);
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bool timeout_expired(u64 timeout);
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#define SPINLOCK_ALIGN 64
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typedef struct {
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s64 lock;
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int count;
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} spinlock_t ALIGNED(SPINLOCK_ALIGN);
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#define SPINLOCK_INIT \
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{ \
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-1, 0 \
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}
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#define DECLARE_SPINLOCK(n) spinlock_t n = SPINLOCK_INIT;
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void spin_init(spinlock_t *lock);
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void spin_lock(spinlock_t *lock);
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void spin_unlock(spinlock_t *lock);
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#define mdelay(m) udelay((m)*1000)
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#define panic(fmt, ...) \
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do { \
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debug_printf(fmt, ##__VA_ARGS__); \
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flush_and_reboot(); \
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} while (0)
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static inline int poll32(u64 addr, u32 mask, u32 target, u32 timeout)
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{
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while (--timeout > 0) {
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u32 value = read32(addr) & mask;
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if (value == target)
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return 0;
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udelay(1);
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}
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return -1;
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}
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typedef u64(generic_func)(u64, u64, u64, u64, u64);
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struct vector_args {
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generic_func *entry;
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u64 args[5];
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bool restore_logo;
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};
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extern u32 board_id, chip_id;
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extern struct vector_args next_stage;
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void deep_wfi(void);
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bool is_heap(void *addr);
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#endif
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