mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-12-12 15:42:27 +00:00
231 lines
7.1 KiB
C
231 lines
7.1 KiB
C
/* SPDX-License-Identifier: MIT */
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#include "chickens.h"
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#include "cpu_regs.h"
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#include "uart.h"
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#include "utils.h"
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/* Part IDs in MIDR_EL1 */
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#define MIDR_PART_T8181_ICESTORM 0x20
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#define MIDR_PART_T8181_FIRESTORM 0x21
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#define MIDR_PART_T8103_ICESTORM 0x22
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#define MIDR_PART_T8103_FIRESTORM 0x23
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#define MIDR_PART_T6000_ICESTORM 0x24
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#define MIDR_PART_T6000_FIRESTORM 0x25
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#define MIDR_PART_T6001_ICESTORM 0x28
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#define MIDR_PART_T6001_FIRESTORM 0x29
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#define MIDR_REV_LOW GENMASK(3, 0)
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#define MIDR_PART GENMASK(15, 4)
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#define MIDR_REV_HIGH GENMASK(23, 20)
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static void init_common_icestorm(void)
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{
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// "Sibling Merge in LLC can cause UC load to violate ARM Memory Ordering Rules."
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reg_set(SYS_IMP_APL_HID5, HID5_DISABLE_FILL_2C_MERGE);
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reg_clr(SYS_IMP_APL_EHID9, EHID9_DEV_THROTTLE_2_ENABLE);
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// "Prevent store-to-load forwarding for UC memory to avoid barrier ordering
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// violation"
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reg_set(SYS_IMP_APL_EHID10, HID10_FORCE_WAIT_STATE_DRAIN_UC | HID10_DISABLE_ZVA_TEMPORAL_TSO);
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// FIXME: do we actually need this?
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reg_set(SYS_IMP_APL_EHID20, EHID20_TRAP_SMC);
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}
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static void init_common_firestorm(void)
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{
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reg_set(SYS_IMP_APL_HID0, HID0_SAME_PG_POWER_OPTIMIZATION);
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// FIXME: do we actually need this?
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reg_set(SYS_IMP_APL_HID1, HID1_TRAP_SMC);
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reg_clr(SYS_IMP_APL_HID3, HID3_DEV_PCIE_THROTTLE_ENABLE | HID3_DISABLE_ARBITER_FIX_BIF_CRD);
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// "Post-silicon tuning of STNT widget contiguous counter threshold"
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reg_mask(SYS_IMP_APL_HID4, HID4_STNT_COUNTER_THRESHOLD_MASK, HID4_STNT_COUNTER_THRESHOLD(3));
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// "Sibling Merge in LLC can cause UC load to violate ARM Memory Ordering Rules."
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reg_set(SYS_IMP_APL_HID5, HID5_DISABLE_FILL_2C_MERGE);
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reg_set(SYS_IMP_APL_HID9, HID9_TSO_ALLOW_DC_ZVA_WC);
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reg_set(SYS_IMP_APL_HID11, HID11_DISABLE_LD_NT_WIDGET);
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// "configure dummy cycles to work around incorrect temp sensor readings on
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// NEX power gating"
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reg_mask(SYS_IMP_APL_HID13, HID13_PRE_CYCLES_MASK, HID13_PRE_CYCLES(4));
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// Best bit names...
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// Maybe: "RF bank and Multipass conflict forward progress widget does not
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// handle 3+ cycle livelock"
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reg_set(SYS_IMP_APL_HID16, HID16_SPAREBIT0 | HID16_SPAREBIT3 | HID16_ENABLE_MPX_PICK_45 |
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HID16_ENABLE_MP_CYCLONE_7);
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}
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static void init_m1_icestorm(void)
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{
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init_common_icestorm();
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reg_set(SYS_IMP_APL_EHID20, EHID20_FORCE_NONSPEC_IF_OLDEST_REDIR_VALID_AND_OLDER |
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EHID20_FORCE_NONSPEC_IF_SPEC_FLUSH_POINTER_NE_BLK_RTR_POINTER);
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reg_mask(SYS_IMP_APL_EHID20, EHID20_FORCE_NONSPEC_TARGETED_TIMER_SEL_MASK,
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EHID20_FORCE_NONSPEC_TARGETED_TIMER_SEL(3));
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}
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static void init_m1_firestorm(void)
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{
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init_common_firestorm();
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// "Cross-beat Crypto(AES/PMUL) ICache fusion is not disabled for branch
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// uncondtional "recoded instruction."
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reg_set(SYS_IMP_APL_HID0, HID0_FETCH_WIDTH_DISABLE | HID0_CACHE_FUSION_DISABLE);
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reg_set(SYS_IMP_APL_HID7, HID7_FORCE_NONSPEC_IF_STEPPING |
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HID7_FORCE_NONSPEC_IF_SPEC_FLUSH_POINTER_INVALID_AND_MP_VALID);
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reg_mask(SYS_IMP_APL_HID7, HID7_FORCE_NONSPEC_TARGET_TIMER_SEL_MASK,
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HID7_FORCE_NONSPEC_TARGET_TIMER_SEL(3));
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reg_set(SYS_IMP_APL_HID9, HID9_TSO_SERIALIZE_VLD_MICROOPS | HID9_FIX_BUG_51667805);
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reg_set(SYS_IMP_APL_HID18, HID18_HVC_SPECULATION_DISABLE);
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reg_clr(SYS_IMP_APL_HID21, HID21_ENABLE_LDREX_FILL_REPLY);
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}
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static void init_t8103_firestorm(int rev)
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{
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init_m1_firestorm();
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reg_mask(SYS_IMP_APL_HID6, HID6_UP_CRD_TKN_INIT_C2_MASK, HID6_UP_CRD_TKN_INIT_C2(0));
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if (rev >= 0x10) {
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reg_set(SYS_IMP_APL_HID4,
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HID4_ENABLE_LFSR_STALL_LOAD_PIPE_2_ISSUE | HID4_ENABLE_LFSR_STALL_STQ_REPLAY);
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reg_set(SYS_IMP_APL_HID9, HID9_FIX_BUG_55719865);
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reg_set(SYS_IMP_APL_HID11, HID11_ENABLE_FIX_UC_55719865);
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}
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if (rev == 0x11)
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reg_set(SYS_IMP_APL_HID1, HID1_ENABLE_MDSB_STALL_PIPELINE_ECO | HID1_ENABLE_BR_KILL_LIMIT);
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if (rev >= 0x11)
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reg_set(SYS_IMP_APL_HID18, HID18_SPAREBIT17);
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}
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static void init_t6000_firestorm(int rev)
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{
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init_m1_firestorm();
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reg_set(SYS_IMP_APL_HID9, HID9_FIX_BUG_55719865);
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reg_set(SYS_IMP_APL_HID11, HID11_ENABLE_FIX_UC_55719865);
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if (rev >= 0x10) {
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reg_set(SYS_IMP_APL_HID1, HID1_ENABLE_MDSB_STALL_PIPELINE_ECO | HID1_ENABLE_BR_KILL_LIMIT);
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reg_set(SYS_IMP_APL_HID4,
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HID4_ENABLE_LFSR_STALL_LOAD_PIPE_2_ISSUE | HID4_ENABLE_LFSR_STALL_STQ_REPLAY);
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reg_set(SYS_IMP_APL_HID18, HID18_SPAREBIT17);
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}
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}
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static void init_t6001_firestorm(int rev)
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{
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init_m1_firestorm();
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reg_set(SYS_IMP_APL_HID1, HID1_ENABLE_MDSB_STALL_PIPELINE_ECO);
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reg_set(SYS_IMP_APL_HID4,
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HID4_ENABLE_LFSR_STALL_LOAD_PIPE_2_ISSUE | HID4_ENABLE_LFSR_STALL_STQ_REPLAY);
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reg_set(SYS_IMP_APL_HID9, HID9_FIX_BUG_55719865);
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reg_set(SYS_IMP_APL_HID11, HID11_ENABLE_FIX_UC_55719865);
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if (rev >= 0x10) {
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reg_set(SYS_IMP_APL_HID1, HID1_ENABLE_BR_KILL_LIMIT);
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reg_set(SYS_IMP_APL_HID18, HID18_SPAREBIT17);
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}
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}
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const char *init_cpu(void)
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{
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const char *cpu = "Unknown";
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msr(OSLAR_EL1, 0);
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/* This is performed unconditionally on all cores (necessary?) */
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if (is_ecore())
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reg_set(SYS_IMP_APL_EHID4, HID4_DISABLE_DC_MVA | HID4_DISABLE_DC_SW_L2_OPS);
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else
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reg_set(SYS_IMP_APL_HID4, HID4_DISABLE_DC_MVA | HID4_DISABLE_DC_SW_L2_OPS);
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uint64_t midr = mrs(MIDR_EL1);
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int part = FIELD_GET(MIDR_PART, midr);
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int rev = (FIELD_GET(MIDR_REV_HIGH, midr) << 4) | FIELD_GET(MIDR_REV_LOW, midr);
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printf(" CPU part: 0x%x rev: 0x%x\n", part, rev);
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switch (part) {
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case MIDR_PART_T8103_FIRESTORM:
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cpu = "M1 Firestorm";
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init_t8103_firestorm(rev);
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break;
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case MIDR_PART_T6000_FIRESTORM:
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cpu = "M1 Pro Firestorm";
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init_t6000_firestorm(rev);
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break;
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case MIDR_PART_T6001_FIRESTORM:
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cpu = "M1 Max Firestorm";
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init_t6001_firestorm(rev);
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break;
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case MIDR_PART_T8103_ICESTORM:
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cpu = "M1 Icestorm";
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init_m1_icestorm();
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break;
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case MIDR_PART_T6000_ICESTORM:
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cpu = "M1 Pro Icestorm";
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init_m1_icestorm();
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break;
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case MIDR_PART_T6001_ICESTORM:
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cpu = "M1 Max Icestorm";
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init_m1_icestorm();
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break;
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default:
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uart_puts(" Unknown CPU type");
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break;
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}
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int core = mrs(MPIDR_EL1) & 0xff;
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// Unknown, related to SMP?
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msr(s3_4_c15_c5_0, core);
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msr(SYS_IMP_APL_AMX_CTL_EL1, 0x100);
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// Enable IRQs (at least necessary on t600x)
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msr(s3_4_c15_c10_4, 0);
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sysop("isb");
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/* Unmask external IRQs, set WFI mode to up (2) */
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reg_mask(SYS_IMP_APL_CYC_OVRD,
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CYC_OVRD_FIQ_MODE_MASK | CYC_OVRD_IRQ_MODE_MASK | CYC_OVRD_WFI_MODE_MASK,
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CYC_OVRD_FIQ_MODE(0) | CYC_OVRD_IRQ_MODE(0) | CYC_OVRD_WFI_MODE(2));
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/* Enable branch prediction state retention across ACC sleep */
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reg_mask(SYS_IMP_APL_ACC_CFG, ACC_CFG_BP_SLEEP_MASK, ACC_CFG_BP_SLEEP(3));
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return cpu;
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}
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