Hector Martin
248011f7a1
apple_regs.json: Correct VM pauth registers
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 21:28:31 +09:00
Hector Martin
920ff59483
exception: Unbork EL1 stack
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 21:14:58 +09:00
Hector Martin
11ef3bb461
proxyutils.py: Allow mrs/msr to pass region (for EL1 etc)
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 20:10:51 +09:00
Hector Martin
757213b7a9
apple_regs.json: Add some EL1 registers for AP
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Still not sure how to enable APSTS_EL12...
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 20:10:34 +09:00
Hector Martin
98839afab0
proxyutils.py: Use keyword-only arguments for msr/msr/inst
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So I stop writing mrs(sysreg, value)...
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 19:02:57 +09:00
Hector Martin
aebda5213a
hv.py: Now gets pretty far into XNU boot
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Next up: mmiotrace
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 19:02:35 +09:00
Hector Martin
9efa91bf87
gxf: Do not disable the MMU around GXF calls
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We are now SPRR compatible.
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 18:31:27 +09:00
Hector Martin
b9ed00c6f3
memory: Initialize SPRR permissions
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 18:16:56 +09:00
Hector Martin
495732ef6a
proxyutils.py: Fix returning from ad-hoc code
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 18:16:13 +09:00
Hector Martin
7fb35a8533
proxyutils.py: Call ad-hoc code in RX EL1 region
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 18:15:35 +09:00
Hector Martin
8af8dadee1
memory: Support L3 mappings, map m1n1 code as RX.
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This replaces the old pagetable code with an adapted version of what
hv_vm.c does, which can handle block and page mappings more
intelligently.
Then, map the m1n1 code section as RX. This allows us to work in modes
where W^X is enforced.
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 18:14:31 +09:00
Hector Martin
3e1ea2d503
memory: Add separate mappings for EL0 data access
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This unborks stack and constant pool accesses from el0_call.
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 17:36:02 +09:00
Hector Martin
7685800b45
heapblock: Assert if not initialized
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 17:33:57 +09:00
Hector Martin
9ffab4ac98
hv_vm.c: Remove stray ;
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 17:33:48 +09:00
Hector Martin
4a918346a8
shell.py: Add only callables to locals, but also sysregs
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-12 21:21:39 +09:00
Hector Martin
4d75ff90ff
proxyutils.py: Support Apple impdef MSR trap decoding
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-12 21:21:09 +09:00
Hector Martin
f56318abc9
hacr_trap_bits.py: Look at ARM standard-but-not regs too
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-12 21:20:51 +09:00
Hector Martin
857d518950
apple_regs.json: Reformat and add many more registers
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-12 21:20:26 +09:00
Hector Martin
9268f83f9f
sysreg.py: Define bitfields for more Apple regs
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-12 21:20:06 +09:00
Hector Martin
5bea278509
sysreg.py: Add sysreg_name() helper
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-12 21:19:50 +09:00
Hector Martin
a519af2ca8
proxyutils.py: Add support for symbolizing addresses
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-12 21:19:19 +09:00
Hector Martin
90872f460e
macho.py: Support loading and importing symbol files
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-12 21:18:12 +09:00
Hector Martin
db9acba268
utils.py: Register: Initialize to 0
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-12 21:17:38 +09:00
Hector Martin
51bafa3c3f
proxyutils.py: Fix silent arg for mrs/msr
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-12 21:17:09 +09:00
Hector Martin
ec5388d6b5
chainload.py: Support SMP when loading XNU
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-12 21:16:33 +09:00
Hector Martin
4e545d0513
adt.py: Improve parsing of reg/ranges & add resolver
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-12 21:16:15 +09:00
Sven Peter
e58c264a07
gxf: add SPRR/GXF proxyclient experiments
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Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-11 15:48:40 +09:00
Sven Peter
34123e33d8
proxyutils: added GuardedHeap
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Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-11 15:48:40 +09:00
Sven Peter
1c604a77c5
gxf: add support for guarded exception levels
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Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-11 15:48:40 +09:00
Sven Peter
2c5b202c99
sysreg: add support for Apple's custom sysregs
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Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-11 15:48:40 +09:00
Sven Peter
9120cb8426
memory: allow to reinit and temporarily disable the MMU
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Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-11 15:48:40 +09:00
Sven Peter
b00c5e6522
utils.h: add msr_sync convenience macros
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Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-11 15:48:40 +09:00
Sven Peter
36efdd2ac3
allow cpu_regs.h to be included in .S files
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Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-11 15:48:40 +09:00
Sven Peter
813e40f4ca
exception_asm.S: skip msr hcr_el2 if not required
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When guarded exception levels are enabled hcr_el2 can no longer be written to from EL2.
A future commit will however use el1_call to jump to GL1. It will setup hcr_el2 before
enabling GXF such that the write doesn't have to happen in el1_call anymore
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-11 15:48:40 +09:00
Sven Peter
148fe31122
exception_asm.S: correctly setup sp for EL1
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The previous code switched SPSel to EL0 but then used eret to
jump to EL1h which uses SP_EL1 instead
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-11 15:48:40 +09:00
Hector Martin
9a7a5c86a5
hv.py: Map only from guest base to RAM top to guest
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This keeps the hypervisor safe, in theory.
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-09 03:25:51 +09:00
Hector Martin
a6287ae68d
proxy.py: Add defaults to hv_translate flag args
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-09 03:25:51 +09:00
Hector Martin
19415bd6a5
run_guest.py: Support setting boot_args
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-09 03:25:51 +09:00
Hector Martin
3fecf181f9
proxyutils.py: Only decode abort/msr info for SYNC exceptions
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-09 03:25:51 +09:00
Hector Martin
9bfe278f52
proxyutils.py: Add disassemble_at() method
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-09 03:25:51 +09:00
Hector Martin
e3d7e569dc
sysreg.py: Define an impdef EC code that Apple seems to use
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-09 03:25:51 +09:00
Hector Martin
6ad3b263a1
macho.py: Add support for loaded section hooks for patching
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-09 03:25:51 +09:00
Hector Martin
ed32cf6328
hv_exc: Add a hacky STEP feature to interrupt guest after a while
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This should eventually be a proper single step feature or something, but
for now...
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-09 03:25:51 +09:00
Hector Martin
bcdafe8d00
hv_vm: Short-circuit hv_translate when MMU is off
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-09 03:25:51 +09:00
Hector Martin
8d5596a1a1
hv_vm: Fix bug when making L2 mappings
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-09 03:25:51 +09:00
Hector Martin
52823eaab6
hv_asm: Turn off PAN on exception entry
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-09 03:25:51 +09:00
Hector Martin
4c043a0f97
memory: Move SCTLR/TCR defines to arm_cpu_regs.h
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-09 03:25:51 +09:00
Hector Martin
aadf54d86f
proxy.py: Add missing FB defines
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Also fix some calls
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-09 03:25:51 +09:00
Hector Martin
f58a9774d2
hv.py: Shut down fb before entering guest
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-08 03:43:59 +09:00
Hector Martin
0203aa6d3d
proxy: Add framebuffer ops
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-08 03:42:21 +09:00