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Author SHA1 Message Date
Asahi Lina
7ad099a5b6 m1n1.trace.agx: Add exploit mitigation 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
6d3e594903 m1n1.hv: Fix read-only or write-only hooks 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
5cacbdc501 m1n1.fw.agx.initdata: Define buffer manager ctl fields better 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
90f4957725 experiments/agx_xtest.py: Here be exploits! 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
3548d4d210 m1n1.fw.ags.microsequence: Add more ops 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
e8377889d2 m1n1.proxyutils: Add 13.0 beta5/6 versions 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
c35168bb88 m1n1.hw.uat: Gracefully handle inaccessible page tables 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
b063fde19a m1n1.hw.uat: Support block maps 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
bfaf358f82 m1n1.agx.render: Add microsequence hooks 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
e49c90a314 m1n1.agx.context: Add GPUMicroSequence.cur_addr() 
This requires that we pre-allocate the buffer

Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
586be52ec5 m1n1.trace.agx: Log structure UAT permissions as meta 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
b4c687ce13 m1n1.hw.uat: Add ioperm() 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
cc1284f264 hv/trace_agx_defer.py: Exclude context ID 1 (compositor) 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
9a8da80e8d m1n1.trace.agx: Add exclude_context_id option 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
9e93bd70e4 m1n1.fw.agx: More compute and blit stuff 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
074892377c m1n1.fw.agx: Fix some more sequence number-ish field names 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
b7fb8d98d8 m1n1.agx: Increase available VM size and reduce usage 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
25813d91b4 m1n1.trace.agx: Disable RegionC tracing 
The atomic stuff breaks with Linux right now...

Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
3e572aba4a m1n1.fw.dcp.ipc: Add compression info struct 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
813c545509 m1n1.fw.agx: Compute struct fixes for 13.2 
Assuming these apply at 13.0b4 too...

Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
f01a62b7a1 m1n1.fw.agx.cmdqueue: Misc fixes 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
1400b50157 m1n1.fw.agx: Initial 13.2 structure changes 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
e22d2fe049 m1n1.hw.agx: Fix fault status register fields 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
e7dee84c3a m1n1.trace.agx: Misc TA/3D dump changes 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
7e49d104ea m1n1.trace.agx: Add compute tracing 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
8fba6118ce m1n1.fw.agx: Add missing compute stuff 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
89e3fcb2ab m1n1.trace.agx: Fix delayed ring buffer fetches 
This should solve the issue where we see commands that the GPU has
already processed.

Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
37f9c5149c m1n1.proxyutils/constructutils: Add missing versions 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
5d5fa70efa firmware: Add 13.1/13.2 to version list 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
3117cdef99 m1n1.fw.agx: Fixes for 13.0b4 support 
Found while adding 13.2, but almost certainly mistakes from back when we
did 13.0b4.

Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Asahi Lina
91e0809063 m1n1.fw.agx: Misc initdata/etc fixes 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-03-06 15:15:17 +09:00
Janne Grunau
583f290b2b Add a space between '//' and '#' to satisfy clang-format 15 
Signed-off-by: Janne Grunau <j@jannau.net>
 2023-02-02 09:51:08 +09:00
Janne Grunau
5f3bd50b4a experiments/dart_dump.py: Fix register dump after 183991ca19 
Fixes: 183991ca19 ("m1n1.hw.dart: Hide all DART variants behind common interface")
Signed-off-by: Janne Grunau <j@jannau.net>
 2023-02-02 09:50:56 +09:00
Janne Grunau
c8c0bd5dc5 display: Check if FB IOVA is available on dart-disp0 
Fixes a copy and paste error in 1b5dee2496 checking dart-dcp twice.

Fixes: 1b5dee2496 ("display: Map the framebuffer if it is not mapped")
Signed-off-by: Janne Grunau <j@jannau.net>
 2023-02-02 09:50:33 +09:00
Janne Grunau
4e7398e3a8 display: Start scanning for fb IOVA at vm-base 
Required for M2 devices as the M2 Mac mini.

Signed-off-by: Janne Grunau <j@jannau.net>
 2023-02-02 09:50:33 +09:00
Janne Grunau
bff8aa647c dcp: Offset temporary IOVA space from vm-base 
Required on M2 devices.

Signed-off-by: Janne Grunau <j@jannau.net>
 2023-02-02 09:50:33 +09:00
Janne Grunau
7e33a578d8 rtkit: Extend IOVA to 36-bit 
Required for DCP on M2.

Signed-off-by: Janne Grunau <j@jannau.net>
 2023-02-02 09:50:33 +09:00
Janne Grunau
f68a842ab7 rtkit: Apply "asc-dram-mask" consistently 
Required for DCP on M2 which requires 36-bit IOVA space.

Signed-off-by: Janne Grunau <j@jannau.net>
 2023-02-02 09:50:33 +09:00
Janne Grunau
6466f8dec8 dcp: Parse dart SID for DCP 
Required for M2 which for which the dice showed "5".

Signed-off-by: Janne Grunau <j@jannau.net>
 2023-02-02 09:50:33 +09:00
Janne Grunau
8af2489d84 dart: Increase IO address space to 36-bit 
This address space a single TTBR can hold with a 16k page size. Required
for DCP on M2.

Signed-off-by: Janne Grunau <j@jannau.net>
 2023-02-02 09:50:33 +09:00
Janne Grunau
93abc760b2 dart: Add checks to dart_translate_internal() 
Previous assumptions are not longer true with dart8110 on M2.

Signed-off-by: Janne Grunau <j@jannau.net>
 2023-02-02 09:50:33 +09:00
Janne Grunau
c3c29bbd92 dart: Allow SIDs != 0 in dart_setup_pt_region() 
Required for dart-dcp on M2 and M2 Pro/Max.

Signed-off-by: Janne Grunau <j@jannau.net>
 2023-02-02 09:50:33 +09:00
Janne Grunau
72cdec0e31 dart: Use "vm-base" as start when installing L2 tables 
Additional L2 tables for dart-dcp/disp0 need to be from carveout memory
so they can kept after m1n1 exist. iboot has "pt-region-X" and "l2-tt-X"
in the ADT. For DCP on M2 we have to start installing them at "vm-base"
which is 0x8_0000_0000.
This probably causes problems on M2 Pro which uses 1 << 40 as vm-base
for dart-dcp0.

Signed-off-by: Janne Grunau <j@jannau.net>
 2023-02-02 09:50:33 +09:00
Sasha Finkelstein
d110da1e75 copy the touchscreen calibration 
Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com>
 2023-01-28 21:58:44 +09:00
Sven Peter
90d0cd6b89 kboot: Copy ACIO tunables and DROM data 
Signed-off-by: Sven Peter <sven@svenpeter.dev>
 2023-01-28 10:56:03 +09:00
Janne Grunau
2b4ed4abbf hv/trace_cd3217: Add tracing for TI/Apple cd3217 USB type C controller 
Interface (as used by macOS) is simple enough to skip register
definitions.

Signed-off-by: Janne Grunau <j@jannau.net>
 2023-01-28 10:49:04 +09:00
Janne Grunau
6f4c53279e hv/trace_dcp.py: Add support for for M2 
Signed-off-by: Janne Grunau <j@jannau.net>
 2023-01-28 10:48:46 +09:00
Janne Grunau
aaa04cfaba m1n1.trace.asc: Support tracing of a DART SID != 0 
Required for DCP on M2.

Signed-off-by: Janne Grunau <j@jannau.net>
 2023-01-28 10:48:46 +09:00
Janne Grunau
f8964ed0f9 m1n1.fw.asc: Increase DVA size to 36-bits 
A single TTBR covers 36-bit address space with 16k pages. Necessary for
DCP on M2.

Signed-off-by: Janne Grunau <j@jannau.net>
 2023-01-28 10:48:46 +09:00
Janne Grunau
39f933ec1f m1n1.fw.dcp.dcpep: DCPEp_SetShmem allows to query Shmem 
When used with FLAG = 0, IOMFB replies with the current Shmem IOVA. It
is NULL on the first call and keeps the last set value. Updating it
seems to work without issues after shutdown.

Signed-off-by: Janne Grunau <j@jannau.net>
 2023-01-28 10:48:46 +09:00