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m1n1.trace.agx: Fix delayed ring buffer fetches

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This should solve the issue where we see commands that the GPU has
already processed.

Signed-off-by: Asahi Lina <lina@asahilina.net>
This commit is contained in:
Asahi Lina 2023-01-20 16:26:09 +09:00
parent 37f9c5149c
commit 89e3fcb2ab
1 changed files with 5 additions and 4 deletions
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9
proxyclient/m1n1/trace/agx.py
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@ -121,7 +121,7 @@ class ChannelTracer(Reloadable):
if off == self.WPTR:
if self.verbose:
self.log(f"RD [{evt.addr:#x}] WPTR[{ring}] = {evt.data:#x}")
self.poll_ring(ring)
self.poll_ring(ring, evt.data)
elif off == self.RPTR:
if self.verbose:
self.log(f"RD [{evt.addr:#x}] RPTR[{ring}] = {evt.data:#x}")
@ -139,7 +139,7 @@ class ChannelTracer(Reloadable):
if off == self.WPTR:
if self.verbose:
self.log(f"WR [{evt.addr:#x}] WPTR[{ring}] = {evt.data:#x}")
self.poll_ring(ring)
self.poll_ring(ring, evt.data)
elif off == self.RPTR:
if self.verbose:
self.log(f"WR [{evt.addr:#x}] RPTR[{ring}] = {evt.data:#x}")
@ -158,11 +158,12 @@ class ChannelTracer(Reloadable):
for i in range(self.ring_count):
self.poll_ring(i)
def poll_ring(self, ring):
def poll_ring(self, ring, tail=None):
msgcls, size, count = self.channel.ring_defs[ring]
cur = self.state.tail[ring]
tail = self.channel.state[ring].WRITE_PTR.val
if tail is None:
tail = self.channel.state[ring].WRITE_PTR.val
if tail >= count:
raise Exception(f"Message index {tail:#x} >= {count:#x}")
if cur != tail: