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1186 commits

Author SHA1 Message Date
Asahi Lina
7a92257d30 m1n1.agx.render: Change heap size to 0x200 
This seems to be the AGX value

Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-01-20 18:18:13 +09:00
Asahi Lina
e774b5c521 m1n1.trace.agx: Log hook writes 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-01-20 18:18:13 +09:00
Asahi Lina
8e77f8f49f m1n1.fw.agx.channels: Do not require contiguous pages for channel state 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2023-01-20 18:18:13 +09:00
Martin Povišer
2cb6cb46ca tools/run_guest.py: Add -v option for attaching 9P virtio exports 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 17:25:25 +09:00
Martin Povišer
93c20e9395 m1n1.hv: Allocate virtio resources if unspecified 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 17:25:25 +09:00
Martin Povišer
020d86a23f m1n1.utils: Fix len() overflow in RangeMap 
This is to fix

  OverflowError: Python int too large to convert to C ssize_t

in case the upper bound of a range is 1<<64.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 17:25:25 +09:00
Martin Povišer
c760e02388 hv: Insert attached virtios into ADT 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 17:25:25 +09:00
Martin Povišer
d94f918433 m1n1.adt: Add to_bus_addr() method 
So that one knows what to put in reg properties.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 17:25:25 +09:00
Martin Povišer
6f460b1f6a m1n1.adt: Add create_node() method 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 17:25:25 +09:00
Martin Povišer
2b33d7f801 m1n1.adt: Implement 'in' keyword on ADT nodes 
So that one can check for children, like:

  >>> "/arm-io/aic" in u.adt
  True

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 17:25:25 +09:00
Martin Povišer
0249d04a4b m1n1.adt: Add missing 'sys' import 
Used for sys.stderr later on.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 17:25:25 +09:00
Martin Povišer
6661ab14d0 hv: Add 9P virtio peripheral 
Add some minimal implementation of virtio peripherals. At the level
of on-target hypervisor code we implement the MMIO layout and
maintain virtqueues. Once a buffer is available, we break into the
host proxyclient to deal with it.

Specific device-classes of the virtio spec ought to be implemented in
the proxyclient. Here the one device implemented is 9P transport,
exporting the m1n1 source directory.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 17:25:25 +09:00
Hector Martin
586157b8bf experiments/smc_watcher.py: new experiment 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2022-12-26 15:07:52 +09:00
Sasha Finkelstein
8c2ad9ada6 Add z2 touch panel tracing 
Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com>
 2022-12-24 20:45:19 +09:00
Asahi Lina
87fa247d9b m1n1.fw.agx.microsequence: Identify visibility_result_buffer field 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
9ebc38ca73 m1n1.trace.agx: Fix UAT TTBR PT size 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
1b9cb35104 experiments/agx_*.py: Autodetect FW version and GPU rev 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
2b0e022b78 m1n1.agx: Port rendering to G14 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
696cdee114 m1n1.agx.initdata: Port to G14G 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
80266ff93e m1n1.constructutils: Unify version conditional syntax with Rust 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
82a9bf3c26 hv/trace_agx_pwr.py: Cleanup 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
9360a92cdc m1n1/trace/agx.py: Add SGXTracer 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
0a57f45805 m1n1.hw.agx: Add chip info regs 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
e1752306c5 m1n1.fw.agx.initdata: Fix a bunch of fields 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
2dab8e352a m1n1.agx.render: Misc tiling related fixes 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
9e65bd527b experiments/agx_{parallel,renderframe}.py: Misc fixes 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
25e1644858 m1n1.adt: Add mtr-polynom-fuse-agx parsing 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
fbc04995ab tools/chainload.py: Fix chainloading of xnu 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
6e99fde8f2 hv/trace_all_more.py: Trace more stuff 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
10d772f743 hv/trace_agx_pwr.py: Messing with pstates 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
34b883318c m1n1.fw.agx.initdata: Make somethings Dec 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
e4810a452d m1n1.utils: Add align_pot() 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
7b63613945 m1n1.agx.render: Always enable Z compression 
This seems to be required on t600x...

Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
05ece42eba m1n1.agx.render: Better t600x support 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
bcd3d0274d m1n1.agx.initdata: Work out all the ADT relationships 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
d265abc90c m1n1.adt: Fixes for adding properties 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
808baf22df m1n1.agx: Initial T600x port 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:10 +09:00
Asahi Lina
5a73bd6476 hv/trace_agx_pwr.py: New HV experiment 
This is intended to reverse-engineer the macOS driver's power scale
calculations.

Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:17:07 +09:00
Asahi Lina
02d9fdc6a0 m1n1.trace.agx: Add after_init_hook 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:15:55 +09:00
Asahi Lina
e50be4bf0d experiments/agx_tlb.py: Misc tracing changes 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:15:55 +09:00
Asahi Lina
29ee0d5d32 m1n1.hv: Don't catch SystemExit from tracers/shells 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:15:55 +09:00
Asahi Lina
b4d5ff7520 m1n1.agx: Add printing IRQs 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:15:55 +09:00
Asahi Lina
2fe37d6dfa m1n1.fw.agx: Misc field renames & fixes 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:15:55 +09:00
Asahi Lina
b4a19572f2 m1n1.fw.agx.handoff: Add CUR_CTX field 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:15:55 +09:00
Asahi Lina
3aa2be6489 m1n1.hw.uat: Flushing cleanup 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:15:55 +09:00
Asahi Lina
f92be5a076 experiments/agx_parallel.py: Uncomment some power-related tracers 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:15:55 +09:00
Asahi Lina
f6dad68156 m1n1.fw.agx.initdata: Disable KTrace by default 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:15:55 +09:00
Asahi Lina
20fce92280 m1n1.trace.agx: Disable some hex dumps 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:15:55 +09:00
Asahi Lina
b8bf3f485e m1n1.trace.agx: Various UAT related improvements 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:15:55 +09:00
Asahi Lina
a097e5b744 m1n1.trace.agx: Instantiate SGXRegs 
Signed-off-by: Asahi Lina <lina@asahilina.net>
 2022-12-04 13:15:55 +09:00