mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-22 06:33:03 +00:00
m1n1.agx.initdata: Port to G14G
Signed-off-by: Asahi Lina <lina@asahilina.net>
This commit is contained in:
parent
80266ff93e
commit
696cdee114
2 changed files with 234 additions and 64 deletions
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@ -36,7 +36,30 @@ def build_iomappings(agx, chip_id):
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IOMapping(), #
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IOMapping(), #
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]
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elif chip_id in (0x6001, 0x6002):
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elif chip_id == 0x8112:
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return [
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iomap(0x204d00000, 0x14000, 0x14000, 1), # Fender
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iomap(0x20e100000, 0x4000, 0x4000, 0), # AICTimer
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iomap(0x23b0c4000, 0x4000, 0x4000, 1), # AICSWInt
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iomap(0x204000000, 0x20000, 0x20000, 1), # RGX
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IOMapping(), # UVD
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IOMapping(), # unused
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IOMapping(), # DisplayUnderrunWA
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iomap(0x23b2c0000, 0x1000, 0x1000, 0), # AnalogTempSensorControllerRegs
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IOMapping(), # PMPDoorbell
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iomap(0x204d80000, 0x8000, 0x8000, 1), # MetrologySensorRegs
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iomap(0x204d61000, 0x1000, 0x1000, 1), # GMGIFAFRegs
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iomap(0x200000000, 0xd6400, 0xd6400, 1), # MCache registers
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IOMapping(), # AICBankedRegisters
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IOMapping(), # PMGRScratch
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IOMapping(), # NIA Special agent idle register die 0
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IOMapping(), # NIA Special agent idle register die 1
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iomap(0x204e00000, 0x10000, 0x10000, 0), # CRE registers
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iomap(0x27d050000, 0x4000, 0x4000, 0), # Streaming codec registers
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iomap(0x23b3d0000, 0x1000, 0x1000, 0), #
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iomap(0x23b3c0000, 0x1000, 0x1000, 0), #
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]
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elif chip_id in (0x6000, 0x6001, 0x6002):
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mcc_cnt = {0x6002: 16, 0x6001: 8, 0x6000: 4}
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return [
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iomap(0x404d00000, 0x1c000, 0x1c000, 1), # Fender
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@ -73,12 +96,14 @@ CHIP_INFO = {
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unk_924 = [[0] * 8] * 8,
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unk_e48 = [[0] * 8] * 8,
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unk_e24 = 112,
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gpu_fast_die0_sensor_mask64 = 0x12,
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gpu_fast_die0_sensor_mask64_alt = 0x12,
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gpu_fast_die0_sensor_present = 0x01,
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shared1_tab = [
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-1, 0x7282, 0x50ea, 0x370a, 0x25be, 0x1c1f, 0x16fb
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] + ([-1] * 9),
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shared2_tab = [0x800, 0x1555, -1, -1, -1, -1, -1, -1],
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] + ([-1] * 10),
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shared1_a4 = 0xffff,
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shared2_tab = [0x800, 0x1555, -1, -1, -1, -1, -1, -1, 0, 0],
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shared2_unk_508 = 0xc0007,
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unk_3cf4 = [1000.0, 0, 0, 0, 0, 0, 0, 0],
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unk_3d14 = [45.0, 0, 0, 0, 0, 0, 0, 0],
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@ -86,10 +111,12 @@ CHIP_INFO = {
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hwdb_4e0 = 0,
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hwdb_534 = 0,
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num_cores = 8,
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hwdb_560 = 11,
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hwdb_564 = 4,
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gpu_core = 11,
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gpu_rev = 4,
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hwdb_ab8 = 0x48,
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hwdb_abc = 0x8,
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hwdb_b30 = 0,
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rel_max_powers = [0, 19, 26, 38, 60, 87, 100],
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),
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0x6001: Container(
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chip_id = 0x6001,
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@ -106,10 +133,12 @@ CHIP_INFO = {
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13, 13, 13, 13, 0, 0, 0, 0,
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]],
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unk_e24 = 125,
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gpu_fast_die0_sensor_mask64 = 0x80808080,
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gpu_fast_die0_sensor_mask64_alt = 0x90909090,
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gpu_fast_die0_sensor_present = 0x0f,
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shared1_tab = [0] + ([0xffff] * 15),
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shared2_tab = [-1, -1, -1, -1, 0x2aa, 0xaaa, -1, -1],
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shared1_tab = [0] + ([0xffff] * 16),
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shared1_a4 = 0xffff,
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shared2_tab = [-1, -1, -1, -1, 0x2aa, 0xaaa, -1, -1, 0, 0],
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shared2_unk_508 = 0xcc00001,
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unk_3cf4 = [1314.0, 1330.0, 1314.0, 1288.0, 0, 0, 0, 0],
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unk_3d14 = [21.0, 21.0, 22.0, 21.0, 0, 0, 0, 0],
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@ -122,10 +151,12 @@ CHIP_INFO = {
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hwdb_4e0 = 4,
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hwdb_534 = 1,
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num_cores = 32,
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hwdb_560 = 13,
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hwdb_564 = 5,
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gpu_core = 13,
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gpu_rev = 5,
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hwdb_ab8 = 0x2084,
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hwdb_abc = 0x80,
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hwdb_b30 = 0,
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rel_max_powers = [0, 15, 20, 27, 36, 52, 100],
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),
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0x6002: Container(
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chip_id = 0x6002,
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@ -143,10 +174,12 @@ CHIP_INFO = {
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13, 13, 13, 13, 13, 13, 13, 13,
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]],
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unk_e24 = 125,
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gpu_fast_die0_sensor_mask64 = 0x8080808080808080,
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gpu_fast_die0_sensor_mask64_alt = 0x9090909090909090,
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gpu_fast_die0_sensor_present = 0xff,
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shared1_tab = [0] + ([0xffff] * 15),
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shared2_tab = [-1, -1, -1, -1, 0x2aa, 0xaaa, -1, -1],
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shared1_tab = [0] + ([0xffff] * 16),
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shared1_a4 = 0xffff,
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shared2_tab = [-1, -1, -1, -1, 0x2aa, 0xaaa, -1, -1, 0, 0],
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shared2_unk_508 = 0xcc00001,
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unk_3cf4 = [1244.0, 1260.0, 1242.0, 1214.0,
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1072.0, 1066.0, 1044.0, 1042.0],
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@ -161,10 +194,48 @@ CHIP_INFO = {
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hwdb_4e0 = 4,
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hwdb_534 = 1,
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num_cores = 64,
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hwdb_560 = 13,
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hwdb_564 = 5,
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gpu_core = 13,
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gpu_rev = 5,
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hwdb_ab8 = 0x2084,
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hwdb_abc = 0x80,
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hwdb_b30 = 0,
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rel_max_powers = [0, 15, 19, 25, 34, 50, 100],
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),
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0x8112: Container(
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chip_id = 0x8112,
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min_sram_volt = 780,
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max_power = 22800,
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max_freq_mhz = 1398,
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unk_87c = 900,
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unk_8cc = 11000,
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unk_924 = [[
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0.0, 0.0, 0.0, 0.0,
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5.3, 0.0, 5.3, 6.6,
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]] + ([[0] * 8] * 7),
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unk_e48 = [[
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0.0, 0.0, 0.0, 0.0,
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5.3, 0.0, 5.3, 6.6,
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]] + ([[0] * 8] * 7),
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unk_e24 = 125,
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gpu_fast_die0_sensor_mask64 = 0x6800,
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gpu_fast_die0_sensor_mask64_alt = 0x6800,
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gpu_fast_die0_sensor_present = 0x02,
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shared1_tab = [0] + ([0xffff] * 16),
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shared1_a4 = 0,
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shared2_tab = [-1, -1, -1, -1, -1, -1, -1, -1, 0xaa5aa, 0],
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shared2_unk_508 = 0xc00000,
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unk_3cf4 = [1920.0, 0, 0, 0, 0, 0, 0, 0],
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unk_3d14 = [74.0, 0, 0, 0, 0, 0, 0, 0],
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unk_118ec = None,
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hwdb_4e0 = 4,
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hwdb_534 = 0,
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num_cores = 10,
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gpu_core = 15,
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gpu_rev = 3,
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hwdb_ab8 = 0x2048,
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hwdb_abc = 0x4000,
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hwdb_b30 = 1,
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rel_max_powers = [0, 18, 27, 37, 52, 66, 82, 96, 100],
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),
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}
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def build_initdata(agx):
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@ -191,7 +262,7 @@ def build_initdata(agx):
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regionB.stats_cp = agx.kobj.new_buf(0x980, "RegionB.unkptr_180").push()
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# size: 0x3b80, few floats, few ints, needed for init
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regionB.hwdata_a = agx.kobj.new(AGXHWDataA(sgx, chip_info), track=False).push()
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regionB.hwdata_a = agx.kobj.new(AGXHWDataA(sgx, chip_info), track=False)
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# size: 0x80, empty
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regionB.unk_190 = agx.kobj.new_buf(0x80, "RegionB.unkptr_190").push()
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@ -203,11 +274,12 @@ def build_initdata(agx):
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hwdata = agx.kobj.new(AGXHWDataB(sgx, chip_info), track=False)
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hwdata.io_mappings = build_iomappings(agx, chosen.chip_id)
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# how is this computed?
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perf_levels = [0, 19, 26, 38, 60, 87, 100]
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k = 1.02 #?
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count = sgx.perf_state_count
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table_count = sgx.perf_state_table_count
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base_pstate = sgx.getprop("gpu-perf-base-pstate", 3)
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base_freq = sgx.perf_states[base_pstate].freq
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max_freq = sgx.perf_states[count - 1].freq
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for i in range(count):
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ps = sgx.perf_states[i]
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hwdata.frequencies[i] = ps.freq // 1000000
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@ -222,14 +294,10 @@ def build_initdata(agx):
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regionB.hwdata_a.unk_74[i] = k
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hwdata.unk_9b4[i] = k
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hwdata.rel_max_powers[i] = perf_levels[i]
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hwdata.rel_max_powers[i] = chip_info.rel_max_powers[i]
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hwdata.rel_boost_freqs[i] = max(0, int((ps.freq - base_freq) / (max_freq - base_freq) * 100))
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# Mac Mini t8103
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#hwdata.rel_unk = [0, 0, 0, 0, 36, 73, 100] + [0]*9
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# Mac Studio t6002
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hwdata.rel_unk = [0, 0, 0, 0, 20, 50, 100] + [0]*9
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# Macbook 14" t6001
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#hwdata.rel_unk = [0, 0, 10, 28, 42, 64, 100] + [0]*9
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regionB.hwdata_a.push()
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regionB.hwdata_b = hwdata.push()
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regionB.hwdata_b_addr2 = hwdata._addr
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@ -315,5 +383,5 @@ def build_initdata(agx):
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initdata.regionC.push()
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initdata.push()
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print(initdata.val)
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#print(InitData.parse_stream(agx.uat.iostream(0, initdata._addr)))
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return initdata
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@ -38,8 +38,7 @@ class InitData_FWStatus(ConstructClass):
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class AGXHWDataShared1(ConstructClass):
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subcon = Struct(
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"table" / Array(16, Int32sl),
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"unk_40" / Int32ul,
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"table" / Array(17, Int32sl),
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"unk_44" / HexDump(Bytes(0x60)),
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"unk_a4" / Int32ul,
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"unk_a8" / Int32ul,
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@ -48,19 +47,115 @@ class AGXHWDataShared1(ConstructClass):
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def __init__(self, chip_info):
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super().__init__()
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self.table = chip_info.shared1_tab
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self.unk_40 = 0xffff
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self.unk_44 = bytes(0x60)
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self.unk_a4 = 0xffff
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self.unk_a4 = chip_info.shared1_a4
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self.unk_a8 = 0
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class AGXHWDataShared2Curve(ConstructClass):
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subcon = Struct(
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"unk_0" / Int32ul,
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"unk_4" / Int32ul,
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"t1" / Array(16, Int16sl),
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"t2" / Array(16, Int16sl),
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"t3" / Array(8, Array(16, Int32sl)),
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)
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def __init__(self, unk_0=0, unk_4=0, t1=None, t2=None, t3=None):
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self.unk_0 = unk_0
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self.unk_4 = unk_4
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if not t1:
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self.t1 = [0] * 16
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else:
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self.t1 = t1 + [t1[0]] * (16 - len(t1))
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if not t2:
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self.t2 = [0] * 16
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else:
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self.t2 = t2 + [t2[0]] * (16 - len(t2))
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if t3 is None:
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self.t3 = [[0] * 16] * 8
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else:
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self.t3 = ([(i + [0x3ffffff] * (16 - len(i))) for i in t3] +
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[[0x3ffffff] * 16] * (8 - len(t3)))
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class AGXHWDataShared2T8112(ConstructClass):
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subcon = Struct(
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"unk_0" / Array(5, Int32ul),
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"unk_14" / Int32ul,
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"unk_18" / Array(8, Int32ul),
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"curve1" / AGXHWDataShared2Curve,
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"curve2" / AGXHWDataShared2Curve,
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)
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def __init__(self, chip_info):
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self.unk_0 = [0] * 5
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self.unk_18 = [0] * 8
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if chip_info.chip_id == 0x8112:
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self.unk_14 = 0x6000000
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self.curve1 = AGXHWDataShared2Curve(
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0, 0x20000000,
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[-1], [0x0f07], [[]]
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)
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self.curve2 = AGXHWDataShared2Curve(
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7, 0x80000000,
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[
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-1, 25740, 17429, 12550, 9597, 7910, 6657, 5881, 5421
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], [
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0x0F07, 0x04C0, 0x06C0, 0x08C0,
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0x0AC0, 0x0C40, 0x0DC0, 0x0EC0,
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0x0F80
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], [
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[0x03FFFFFF, 107, 101, 94, 87, 82, 77, 73, 71],
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[0x03FFFFFF, 38240, 36251, 33562,
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31368, 29379, 27693, 26211, 25370],
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[0x03FFFFFF, 123933, 117485, 108771,
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101661, 95217, 89751, 84948, 82222],
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]
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)
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else:
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self.unk_14 = 0
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self.curve1 = AGXHWDataShared2Curve()
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self.curve2 = AGXHWDataShared2Curve()
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class AGXHWDataShared3(ConstructClass):
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subcon = Struct(
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"unk_0" / Int32ul,
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"unk_4" / Int32ul,
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"unk_8" / Int32ul,
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"table" / Array(16, Int32ul),
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"unk_4c" / Int32ul,
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)
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def __init__(self, chip_info):
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if chip_info.chip_id == 0x8112:
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self.unk_0 = 1
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self.unk_4 = 500
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self.unk_8 = 5
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self.table = [
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10700, 10700, 10700, 10700,
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10700, 6000, 1000, 1000,
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1000, 10700, 10700, 10700,
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10700, 10700, 10700, 10700,
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]
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self.unk_4c = 1
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else:
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self.unk_0 = 0
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self.unk_4 = 0
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self.unk_8 = 0
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self.table = [0] * 16
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self.unk_4c = 0
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class AGXHWDataShared2(ConstructClass):
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subcon = Struct(
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"table" / Array(8, Int32sl),
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"unk_20" / HexDump(Bytes(0x8)),
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"table" / Array(10, Int32sl),
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"unk_28" / HexDump(Bytes(0x10)),
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"unk_38" / HexDump(Bytes(0x8)),
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"unk_40" / HexDump(Bytes(0x4c8)),
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"unk_38" / AGXHWDataShared2T8112,
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"unk_500" / Int32ul,
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"unk_504" / Int32ul,
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"unk_508" / Int32ul,
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"unk_50c" / Int32ul,
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"unk_510" / Int32ul,
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)
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def __init__(self, chip_info):
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@ -68,9 +163,12 @@ class AGXHWDataShared2(ConstructClass):
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self.table = chip_info.shared2_tab
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self.unk_20 = bytes(8)
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self.unk_28 = b"\xff" * 16
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self.unk_38 = bytes(8)
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self.unk_40 = bytes(0x4c8)
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self.unk_38 = AGXHWDataShared2T8112(chip_info)
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self.unk_500 = 0
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self.unk_504 = 0
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self.unk_508 = chip_info.shared2_unk_508
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self.unk_50c = 0
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self.unk_510 = 0
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class AGXHWDataA130Extra(ConstructClass):
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subcon = Struct(
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@ -169,7 +267,7 @@ class AGXHWDataA130Extra(ConstructClass):
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self.unk_128 = 600
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self.unk_12c = bytes(0x8c)
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class AGXHWDataT8103(ConstructClass):
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class AGXHWDataT81xx(ConstructClass):
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subcon = Struct(
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"unk_d8c" / Int32ul,
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"unk_d90" / Int32ul,
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@ -189,8 +287,8 @@ class AGXHWDataT8103(ConstructClass):
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"unk_dc8" / Int32ul,
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"unk_dcc" / Int32ul,
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)
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def __init__(self, chip_info):
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if chip_info.chip_id == 0x8103:
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def __init__(self, sgx, chip_info):
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if chip_info.chip_id in (0x8103, 0x8112):
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self.unk_d8c = 0x80000000
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self.unk_d90 = 4
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self.unk_d94 = 0
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@ -207,7 +305,7 @@ class AGXHWDataT8103(ConstructClass):
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self.unk_dc0 = 0
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self.unk_dc4 = 0
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self.unk_dc8 = 0
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self.unk_dcc = 600
|
||||
self.unk_dcc = 100 * sgx.gpu_num_perf_states
|
||||
else:
|
||||
self.unk_d8c = 0
|
||||
self.unk_d90 = 0
|
||||
|
@ -520,7 +618,7 @@ class AGXHWDataA(ConstructClass):
|
|||
"max_pstate_scaled_14" / Int32ul,
|
||||
"unk_d68" / Bytes(0x24),
|
||||
|
||||
"t8103_data" / AGXHWDataT8103,
|
||||
"t81xx_data" / AGXHWDataT81xx,
|
||||
|
||||
"unk_dd0" / HexDump(Bytes(0x40)),
|
||||
Ver("V >= V13_0B4", "unk_e10_0" / AGXHWDataA130Extra),
|
||||
|
@ -540,8 +638,11 @@ class AGXHWDataA(ConstructClass):
|
|||
"hws1" / AGXHWDataShared1,
|
||||
Ver("V >= V13_0B4", "unk_pad1" / HexDump(Bytes(0x20))),
|
||||
"hws2" / AGXHWDataShared2,
|
||||
"unk_3bfc" / Int32ul,
|
||||
"unk_3c00" / HexDump(Bytes(0xa0)),
|
||||
"unk_3c04" / Int32ul,
|
||||
"hws3" / AGXHWDataShared3,
|
||||
"unk_3c58" / HexDump(Bytes(0x3c)),
|
||||
"unk_3c94" / Int32ul,
|
||||
"unk_3c98" / Int64ul,
|
||||
"unk_3ca0" / Int64ul,
|
||||
"unk_3ca8" / Int64ul,
|
||||
"unk_3cb0" / Int64ul,
|
||||
|
@ -610,15 +711,15 @@ class AGXHWDataA(ConstructClass):
|
|||
self.unk_64c = 625
|
||||
self.unk_650 = 0
|
||||
self.pad_654 = 0
|
||||
self.pwr_filter_a_neg = 1 - 1 / sgx.gpu_pwr_filter_time_constant
|
||||
self.pwr_filter_a_neg = 1 - 1 / sgx.getprop("gpu-pwr-filter-time-constant", 313)
|
||||
self.pad_65c = 0
|
||||
self.pwr_filter_a = 1 - self.pwr_filter_a_neg
|
||||
self.pad_664 = 0
|
||||
self.pwr_integral_gain = sgx.gpu_pwr_integral_gain
|
||||
self.pwr_integral_gain = sgx.getprop("gpu-pwr-integral-gain", 0.0202129)
|
||||
self.pad_66c = 0
|
||||
self.pwr_integral_min_clamp = sgx.gpu_pwr_integral_min_clamp
|
||||
self.pwr_integral_min_clamp = sgx.getprop("gpu-pwr-integral-min-clamp", 0)
|
||||
self.max_power_1 = chip_info.max_power
|
||||
self.pwr_proportional_gain = sgx.gpu_pwr_proportional_gain
|
||||
self.pwr_proportional_gain = sgx.getprop("gpu-pwr-proportional-gain", 5.2831855)
|
||||
self.pad_67c = 0
|
||||
self.pwr_pstate_related_k = -self.max_pstate_scaled / chip_info.max_power
|
||||
self.pwr_pstate_max_dc_offset = sgx.gpu_pwr_min_duty_cycle - self.max_pstate_scaled
|
||||
|
@ -645,7 +746,7 @@ class AGXHWDataA(ConstructClass):
|
|||
self.pad_6ec = 0
|
||||
self.ppm_ki_dt = sgx.gpu_ppm_ki * (period_ms / 1000)
|
||||
self.pad_6f4 = 0
|
||||
self.pwr_integral_min_clamp_2 = sgx.gpu_pwr_integral_min_clamp
|
||||
self.pwr_integral_min_clamp_2 = self.pwr_integral_min_clamp
|
||||
if Ver.check("V >= V13_0B4") or chip_info.chip_id != 0x8103:
|
||||
self.unk_6fc = 65536.0
|
||||
else:
|
||||
|
@ -729,10 +830,7 @@ class AGXHWDataA(ConstructClass):
|
|||
self.unk_83c = 0x0
|
||||
self.pad_840 = bytes(0x2c)
|
||||
self.unk_86c = 0x0
|
||||
mask = sgx.getprop("gpu-fast-die0-sensor-mask64", None)
|
||||
if mask is None:
|
||||
mask = sgx.gpu_fast_die0_sensor_mask
|
||||
self.fast_die0_sensor_mask64 = mask
|
||||
self.fast_die0_sensor_mask64 = chip_info.gpu_fast_die0_sensor_mask64
|
||||
self.fast_die0_release_temp_cc = 100 * sgx.getprop("gpu-fast-die0-release-temp", 80)
|
||||
self.unk_87c = chip_info.unk_87c
|
||||
self.unk_880 = 0x4
|
||||
|
@ -835,13 +933,13 @@ class AGXHWDataA(ConstructClass):
|
|||
self.max_pstate_scaled_14 = self.max_pstate_scaled
|
||||
self.unk_d68 = bytes(0x24)
|
||||
|
||||
self.t8103_data = AGXHWDataT8103(chip_info)
|
||||
self.t81xx_data = AGXHWDataT81xx(sgx, chip_info)
|
||||
|
||||
self.unk_dd0 = bytes(0x40)
|
||||
|
||||
self.unk_e10_0 = AGXHWDataA130Extra()
|
||||
self.unk_e10 = bytes(0xc)
|
||||
self.fast_die0_sensor_mask64_2 = mask
|
||||
self.fast_die0_sensor_mask64_2 = chip_info.gpu_fast_die0_sensor_mask64
|
||||
self.unk_e24 = chip_info.unk_e24
|
||||
self.unk_e28 = 1
|
||||
self.unk_e2c = bytes(0x1c)
|
||||
|
@ -856,8 +954,11 @@ class AGXHWDataA(ConstructClass):
|
|||
self.hws1 = AGXHWDataShared1(chip_info)
|
||||
self.unk_pad1 = bytes(0x20)
|
||||
self.hws2 = AGXHWDataShared2(chip_info)
|
||||
self.unk_3bfc = 0
|
||||
self.unk_3c00 = bytes(0xa0)
|
||||
self.unk_3c04 = 0
|
||||
self.hws3 = AGXHWDataShared3(chip_info)
|
||||
self.unk_3c58 = bytes(0x3c)
|
||||
self.unk_3c94 = 0 # flag
|
||||
self.unk_3c98 = 0 # timestamp?
|
||||
self.unk_3ca0 = 0 # timestamp?
|
||||
self.unk_3ca8 = 0
|
||||
self.unk_3cb0 = 0
|
||||
|
@ -868,7 +969,6 @@ class AGXHWDataA(ConstructClass):
|
|||
self.unk_3cd8 = 0
|
||||
self.unk_3ce0_0 = 0
|
||||
|
||||
|
||||
self.unk_3ce0 = 0
|
||||
self.unk_3ce4 = 0
|
||||
self.unk_3ce8 = 1
|
||||
|
@ -1007,8 +1107,8 @@ class AGXHWDataB(ConstructClass):
|
|||
"unk_550" / Int32ul,
|
||||
"unk_554" / Int32ul,
|
||||
"gpu_region_base" / Int64ul,
|
||||
"unk_560" / Int32ul,
|
||||
"unk_564" / Int32ul,
|
||||
"gpu_core" / Int32ul,
|
||||
"gpu_rev" / Int32ul,
|
||||
"num_cores" / Int32ul,
|
||||
"max_pstate" / Int32ul,
|
||||
Ver("V < V13_0B4", "num_pstates" / Int32ul),
|
||||
|
@ -1018,7 +1118,7 @@ class AGXHWDataB(ConstructClass):
|
|||
"unk_9b4" / Array(16, Float32l),
|
||||
"unk_9f4" / Array(16, Int32ul),
|
||||
"rel_max_powers" / Array(16, Dec(Int32ul)),
|
||||
"rel_boost_powers" / Array(16, Dec(Int32ul)),
|
||||
"rel_boost_freqs" / Array(16, Dec(Int32ul)),
|
||||
Ver("V < V13_0B4", "min_sram_volt" / Dec(Int32ul)),
|
||||
Ver("V < V13_0B4", "unk_ab8" / Int32ul),
|
||||
Ver("V < V13_0B4", "unk_abc" / Int32ul),
|
||||
|
@ -1220,8 +1320,8 @@ class AGXHWDataB(ConstructClass):
|
|||
self.unk_550 = 0x0
|
||||
self.unk_554 = 0x1
|
||||
self.gpu_region_base = sgx.gpu_region_base
|
||||
self.unk_560 = chip_info.hwdb_560
|
||||
self.unk_564 = chip_info.hwdb_564
|
||||
self.gpu_core = chip_info.gpu_core
|
||||
self.gpu_rev = chip_info.gpu_rev
|
||||
self.num_cores = chip_info.num_cores
|
||||
self.max_pstate = sgx.gpu_num_perf_states
|
||||
self.num_pstates = sgx.gpu_num_perf_states + 1
|
||||
|
@ -1232,7 +1332,7 @@ class AGXHWDataB(ConstructClass):
|
|||
self.unk_9b4 = [0.] * 16
|
||||
self.unk_9f4 = [0] * 16
|
||||
self.rel_max_powers = [0] * 16
|
||||
self.rel_boost_powers = [0] * 16
|
||||
self.rel_boost_freqs = [0] * 16
|
||||
self.min_sram_volt = chip_info.min_sram_volt
|
||||
self.unk_ab8 = chip_info.hwdb_ab8
|
||||
self.unk_abc = chip_info.hwdb_abc
|
||||
|
@ -1256,7 +1356,7 @@ class AGXHWDataB(ConstructClass):
|
|||
self.unk_b24 = 0x1
|
||||
self.unk_b28 = 0x1
|
||||
self.unk_b2c = 0x1
|
||||
self.unk_b30 = 0x0
|
||||
self.unk_b30 = chip_info.hwdb_b30
|
||||
self.unk_b34 = 0x0
|
||||
self.unk_b38_0 = 1
|
||||
self.unk_b38_4 = 1
|
||||
|
@ -1594,7 +1694,8 @@ class InitData_RegionC(ConstructClass):
|
|||
Ver("V >= V13_0B4", "unk_89f4_c" / HexDump(Bytes(0x50))),
|
||||
"hws1" / AGXHWDataShared1,
|
||||
"hws2" / AGXHWDataShared2,
|
||||
"unk_8fac" / HexDump(Bytes(0x60)),
|
||||
"hws3" / AGXHWDataShared3,
|
||||
"unk_9004" / HexDump(Bytes(8)),
|
||||
Ver("V >= V13_0B4", "unk_900c_0" / HexDump(Bytes(0x28))),
|
||||
"unk_900c" / Int32ul,
|
||||
Ver("V >= V13_0B4", "unk_9010_0" / Int32ul),
|
||||
|
@ -1715,7 +1816,8 @@ class InitData_RegionC(ConstructClass):
|
|||
self.unk_89f4_c = bytes(0x50)
|
||||
self.hws1 = AGXHWDataShared1(chip_info)
|
||||
self.hws2 = AGXHWDataShared2(chip_info)
|
||||
self.unk_8fac = bytes(0x60)
|
||||
self.hws3 = AGXHWDataShared3(chip_info)
|
||||
self.unk_9004 = bytes(8)
|
||||
self.unk_900c_0 = bytes(0x28)
|
||||
self.unk_900c = 1
|
||||
self.unk_9010_0 = 1
|
||||
|
|
Loading…
Reference in a new issue