Commit graph

182 commits

Author SHA1 Message Date
Sven Peter
1314a426e2 proxyclient: add PMGR ops
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-04-11 05:26:29 +09:00
Sven Peter
b31e1265ff pmgr: add functions to enable/disable clocks
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-04-11 05:26:29 +09:00
Sven Peter
95b1cb39fc utils.h: add poll32
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-04-11 05:26:29 +09:00
Sven Peter
bf3830ee6d utils.h: add dma_mb,dma_rmb,dma_wmb
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-04-11 05:26:29 +09:00
Sven Peter
d256b89343 malloc.h: include stddef to ensure size_t is defined
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-04-11 05:26:29 +09:00
Sven Peter
f17a15d19a proxyclient/i2c: experiment with the i2c and ti usb chip
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-04-09 14:47:22 +09:00
Sven Peter
8aa3c69a2d tunables: add tunables_apply_local_addr
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-04-08 20:32:12 +09:00
Sven Peter
a17e64f1e2 tunables: add proxy ops
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-04-08 20:32:12 +09:00
Sven Peter
d73276b0bc tunables: add initial version.
There are at least two types in the ADT related to USB,
but there's a decent chance that there are even more
required for other devices:

 * A simple tunable that applies to a whole device node
   and all its MMIO ranges specified in the "reg" property.
   This one seems to just be mask32.

 * A slightly more complex tunable that applies to a single
   MMIO range specified in the "reg" property. So far I've
   only seen 32 bit masks but the format looks like it should
   also support 8,16 and 64 bit masks.

Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-04-08 20:32:12 +09:00
Sven Peter
1134a4a649 ci: add clang-format check to the CI
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-04-08 20:30:41 +09:00
Sven Peter
ed72fe443c proxyclient/asm.py: allow to override compiler prefix
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-04-05 23:49:25 +09:00
Hector Martin
3a42f80a73 chainload.py: Set up sane EL1 config for timers/IRQs
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-28 19:31:14 +09:00
Hector Martin
cecf51f245 dts: Update with current kernel devicetree, improve build
Now uses the same devicetree source as the kernel, verbatim, with the
required subset of kernel dt includes.

Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-15 02:26:31 +09:00
Hector Martin
35f2b2435e kboot: reserve m1n1 in memory
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-15 02:26:13 +09:00
Hector Martin
70f6bc7514 linux.py: support up to 512MB kernels
Some people apparently have the patience to load KASAN kernels over
serial :-)

Also bump the python-managed heap to 1GB.

Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-08 01:33:43 +09:00
Hector Martin
efa4452a47 Fix libc header dependencies
Turns out we had a bunch of silly dependencies on libc headers that are
not included with freestanding compilers. Fix all this and change the
CFLAGS to exclude libc headers and only include the built-in compiler
path.

Add our own versions of assert.h, errno.h, limits.h, and move malloc.h
and string.h together into a new path used as -isystem, so these headers
can be included using #include <>.

Remove a bunch of other dependencies in third-party code.

Add a strnlen function.

Disable building the libfdt overlay code for now, as it needs a strtoul
implementation. We can throw that in if/when we decide to use overlays.

Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-08 01:31:14 +09:00
Hector Martin
3c514e826c fptest.py: test Apple floating-point controls
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-04 23:22:41 +09:00
Hector Martin
db49cc92f3 hacr_trap_bits.py: figure out HACR_EL2 sysreg traps
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-04 23:20:50 +09:00
Hector Martin
1a880518b0 chainload.py: implement chainloading at EL1
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-04 22:41:06 +09:00
Hector Martin
3bf3613e7d find_all_regs: print EL2-only registers
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-04 22:40:25 +09:00
Hector Martin
ce2038c59c memory: use tlbi vmalle1is
This works at both EL1 and EL2(with VHE) and seems to do the right
thing.

Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-04 22:39:26 +09:00
Hector Martin
b8349819fe Implement calling code as EL1
This works by clearing HCR_EL2.TGE, and then doing essentially the same
thunk/return dance as for EL0 calls. However, since most EL1 exceptions
are not routed to EL2, we install hypercall vectors in EL1 to forward
them to EL2, and then short circuit the exception return to whatever
triggered the original exception.

Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-04 22:10:37 +09:00
Hector Martin
f669237c2a start.S: clean up some junk
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-04 21:27:25 +09:00
Hector Martin
16cff51bd4 exception,memory: s/EL2/EL1/
Since we're in VHE mode, we can pretend to be in EL1 - but this will
allow us to really run in EL1 if we want to in the future.

Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-04 20:31:36 +09:00
Hector Martin
4282cd0578 exception: size tables properly, work around overeager clang-format
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-04 19:52:53 +09:00
Hector Martin
d5acb000f2 kboot: add support for KASLR and bootloader randomness
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-04 19:47:39 +09:00
Hector Martin
8e4b99d75a memory: reformat and shorten MAIR_INDEX to MAIR_IDX
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-04 19:47:37 +09:00
Hector Martin
acf1198fbb timer_test.py: add test of HV/guest timers
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-01 01:47:42 +09:00
Hector Martin
0f2be2c0ee utils.py: unbork inst()
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-03-01 01:45:39 +09:00
Hector Martin
2f959f758c find_all_regs.py: show EL0-accessible registers
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-25 00:33:00 +09:00
Hector Martin
d918b066b6 utils.py: add silent and call arguments to msr/mrs
call allows the caller to override the function used for the function
call, e.g. to use EL0.

Use silent=True for find_all_regs.py

Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-25 00:30:58 +09:00
Hector Martin
3872b1a7da exception: implement el0_call to run code as EL0
This lets us test register access and other features from EL0.

No serious attempt at security is made, but at least EL0 runs off of a
separate stack and can return to EL2 at any time with `brk`; we can
easily implement a guard mode to break straight to EL2 on exception
later if needed.

Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-24 21:48:12 +09:00
Hector Martin
73a85be2b8 memory: prepare for EL0 support
Enable EL0 access to MMIO/etc, but not main RAM, because AArch64
architecturally enforces EL0w ^ EL2x.

Instead, create an alias of main RAM to grant EL0 full permissions,
at 0x80_0000_0000.

Grant EL0 full access to MMIO stuff, since EL2 will never execute
from there.

Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-24 21:48:12 +09:00
Hector Martin
a0960fca81 find_all_regs.py: test writability
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-24 21:48:12 +09:00
Hector Martin
65824016b7 utils.py add silent argument to inst() 2021-02-24 19:01:17 +09:00
Hector Martin
64306e78a0 linux.py: only mask DAIF.IF
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-21 11:55:54 +09:00
Sven Peter
54a147013f chainload.py: compress payload to improve loading time
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-02-20 01:29:46 +09:00
Sven Peter
fa02cc9602 utils.py: add compressed writemem
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-02-20 01:29:46 +09:00
Hector Martin
b7d30250b2 utils: allow inst() to return r0 and take args
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-19 03:25:28 +09:00
Hector Martin
b5cbf7360e exception: handle PMC FIQs
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-18 17:55:55 +09:00
Hector Martin
cf640de6db utils.h: add BIT() macro
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-18 17:55:55 +09:00
Hector Martin
17aca31498 utils.h: move reg_{clr,set,mask} here from chickens.c
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-18 17:55:55 +09:00
Hector Martin
86a7d9c0f3 cpu_regs.h: s/SYS_/SYS_APL_/
This synchronizes the register naming convention with Linux

Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-18 17:55:55 +09:00
Sven Peter
f3eed1c7d7 MMU: correctly map MMIO/PCIe ranges
Previously all MMIO was mapped twice with different attributes
which may or may not lead to strange behaviour when the same
physical range is accessed from both mappings.

We now have a better idea which ranges require nGnRE and nGnRnE
and can just do it correctly instead.

Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-02-18 16:16:55 +09:00
Sebastian Gräßl
ed0bd4aebc tooling: Add container setup for build environment
Signed-off-by: Sebastian Gräßl <mail@bastilian.me>
2021-02-18 16:14:15 +09:00
Sven Peter
870fead39c proxyclient: add ops for writeread{8,16,32,64}
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-02-18 16:12:28 +09:00
Sven Peter
1ccf2e2af5 utils.h: add writeread{8,16,32,64}
These functions all perform a store direcly followed by a load.
This is useful to e.g. useful to find busy bits which might
already be cleared a few cycles after a write.

Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-02-18 16:12:28 +09:00
Sven Peter
24938db17a MMU: use alle2 instead of vmalls12e1is to invalidate TLBs
I can't remember why I used vmalls12e1is but this leads to
the following bug:

  1. Load m1n1 with normal MMU setup
  2. Disable all mappings, recompile and chainload to that m1n1
  3. Everything will work fine for a while even though it should explode
     when enabling the MMU.

This happens becuse there are still stale TLB entries in some cache.

Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-02-15 01:37:39 +09:00
Khoa Hoang
2789b6f3e0 proxyclient: add input support for tty mode
Use miniterm from pyserial for tty passthrough mode

Signed-off-by: Khoa Hoang <admin@khoahoang.com>
2021-02-13 02:48:58 +09:00
Hector Martin
d46d51d7ed exception: fix vtimer FIQ masking
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-11 01:35:23 +09:00