fb_console_reserve_lines() in mmu_shutdown() was causing a blit from the
freed framebuffer, putting heap metadata junk at the top left corner.
Signed-off-by: Hector Martin <marcan@marcan.st>
t8103 and t600x use "asc-dram-mask" in iop-dcp-nub to mask bits out of
DMA addresses. This needs to be used in the firmware mappings
check/remap since the segments have maskable bits sets.
Fixes: 8332e24 ("dcp: Undo carnage from bad stage1 DART code")
Signed-off-by: Janne Grunau <j@jannau.net>
A bug in our DART code was wiping and aliasing page tables. Go through
the segment ranges for DCP and redo any missing mappings. If we redid
any mappings, then PMGR reset DCP so it can recover from having faulted
on the previous boot.
Signed-off-by: Hector Martin <marcan@marcan.st>
We were assuming L2 tables were always allocated consecutively at low
IOVAs. 14.5 broke this, causing all kinds of explosions.
The new code looks for the first unused L2 PT, and also checks whether
the first 2 entries are aliased to latter entries (which is what the old
code caused). If so, it clears them and reallocates them. This doesn't
undo the PT wipe from stage1 though, so downstream code has to redo any
missing mappings...
Signed-off-by: Hector Martin <marcan@marcan.st>
Use a struct instead of global variable to hold the necessary setup
information. This allows executing the setup for both sio instances.
In addition change the status to "okay" so that sio can remain disabled
if the setup fails.
Signed-off-by: Janne Grunau <j@jannau.net>
For some reason the ans node for t602x devices has an empty
"clock-gates" property. Use the MMIO address instead to determine on
which die the device is.
Fixes: 34f49a5 ("nvme: assume die 0 if clock-gates not set")
Signed-off-by: Janne Grunau <j@jannau.net>
M3+ have a new USB power controller and it works over SPMI.
However, the USB ports work (at least within m1n1) if we ignore
this and just init the phys directly.
This detects the case where we are not on an I2C based USB machine,
and initializes the phys directly.
Eventually we should support SPMI properly.
Signed-off-By: Daniel Berlin <dberlin@dberlin.org>
The UART base has moved from the M2 chips.
Everest settings introduce some changes to unknown registers
The MCC data has changed as well.
There is a drive-by change where I discovered what some of the unknown
HID18 bits are and documented them.
Signed-off-by: Daniel Berlin <dberlin@dberlin.org>
Right now, we assume the boot cpu is cpu0. That is not true on m3 max,
where it is CPU 4.
To figure out which CPU is the boot CPU, we check to see which CPU
is running before we start any other CPUs, and record the MPIDR/idx.
Without this patch, four issues happen on m3 max:
1. We try to start the boot CPU again, crashing it
2. We skip the real CPU 0
3. We start m1n1 again on CPU0 when we boot it
4. We enable interrupts on CPU0 because we think it's the primary CPU.
Signed-off-by: Daniel Berlin <dberlin@dberlin.org>
dcpext0 behaves like dcp on M1* devices and can sleep after display
init. This has the advantage of not breaking macOS when starting with an
initialized display.
dcpext* are according to Apple's tech specs slightly more powerful than
dcp. They are advertised as 6K at 60Hz while dcp seems to be limited to
5K at 60Hz.
Signed-off-by: Janne Grunau <j@jannau.net>
Apperently just informative as display init on M2 Ultra in m1n1 worked
as expected despite passing '0' as die number.
Signed-off-by: Janne Grunau <j@jannau.net>
Required for stage 1 loader to allow chainloaded display/dcp experiments
to start with the state left by iboot.
Signed-off-by: Janne Grunau <j@jannau.net>
I only can easily find the T6031/T6034/T8122 values.
If there is a T6030, the value is not in the same place I found these.
Signed-off-by: Daniel Berlin <dberlin@dberlin.org>
If DEBUG is not defined, the compiler doesn't look at the arguments to
dprintf(). This has led to dprintf() bitrotting over time, referring
to variables that no longer exist, or by the wrong type, etc.
Here, I've tried to fix all the dprintf() calls to the best of my
ability, by comparing them to nearby calls that do compile, and
looking through the git history to understand the original intent.
Signed-off-by: Alyssa Ross <hi@alyssa.is>
The dptxport endpoint changed API between 13.3 and 13.5. Nobody is
supposed to run 13.3 OS firmware at this point so do not claim to be
compatible. The DCP linux driver is fixed since a couple of weeks to
accept 13.5 as compat version.
Signed-off-by: Janne Grunau <j@jannau.net>
Only the HDMI port on 14 and 16 inch Macbook Pros needs dcpext and the
dptxport endpoint implemention in the DCP driver supports only the 13.5
firmware. Postpone this for after the fedora release.
Signed-off-by: Janne Grunau <j@jannau.net>
Avoids manually matching pre-mapped memory against "carveout-memory-map"
and maintaining a list of hopefully static carveoout regions.
Leave t8103 and t600x alone for now. Porting dcp over to this a littles
harder since that needs additional handling for regions mapped to
"dart-disp0?".
Signed-off-by: Janne Grunau <j@jannau.net>
Power up display early (fixes HPD sometimes) and delay at least one
frame after swapping before quiescing DCP, otherwise the swap somehow
doesn't complete.
Signed-off-by: Hector Martin <marcan@marcan.st>
stage1 ends up with an ugly Asahi 100% logo on top of a 200% Apple logo.
Let's just clear it so it looks nicer.
Signed-off-by: Hector Martin <marcan@marcan.st>
This works around issues switching to 120Hz mode on systems affected by
the Sonoma situation, and in general it's probably a good idea anyway.
Signed-off-by: Hector Martin <marcan@marcan.st>
It appears that when macOS is set to non-ProMotion mode, DCP firmware
<14.0 booted from DCP firmware 14.0+ needs a delay before modesetting to
complete the modeset properly.
The cases here are:
- Older m1n1 stage1 will, as far as it's concerned, initialize the
display properly, but it won't work. It also misses the retina flag,
since this codepath was intended for external displays. Use the
missing retina flag as a signal to trigger reconfig.
- If installed as stage1, we reconfigure the display as usual, now with
the extra delay. We also set the Retina flag now.
The persistence mechanism for the ProMotion flag is unknown. It doesn't
seem to be nvram. It also doesn't matter if we successfully modeset to
120Hz mode and then reboot, it breaks again, so it's not about the
"current" mode sticking.
Signed-off-by: Hector Martin <marcan@marcan.st>
