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https://github.com/AsahiLinux/m1n1
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memory: Make the RAM base dynamic
For now we compute this as phys_base aligned down to a 4GiB boundary. Hopefully that works for future SoCs too. Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
parent
38fc7a0780
commit
7ff48f6201
3 changed files with 18 additions and 16 deletions
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@ -440,8 +440,8 @@ class GUARD(IntFlag):
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SILENT = 0x100
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REGION_RWX_EL0 = 0x8000000000
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REGION_RW_EL0 = 0x9000000000
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REGION_RX_EL1 = 0xa000000000
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REGION_RW_EL0 = 0xa000000000
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REGION_RX_EL1 = 0xc000000000
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# Uses UartInterface.proxyreq() to send requests to M1N1 and process
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# reponses sent back.
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24
src/memory.c
24
src/memory.c
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@ -37,6 +37,8 @@ extern u8 _stack_top[];
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extern u8 gl1_stack[GL_STACK_SIZE];
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extern u8 gl2_stack[MAX_CPUS][GL_STACK_SIZE];
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uint64_t ram_base = 0;
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static inline u64 read_sctlr(void)
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{
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sysop("isb");
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@ -339,8 +341,8 @@ static void mmu_unmap_carveouts(void)
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uint64_t start = ((uint64_t)read32(mcc_tz_base + TZ_START(i))) << 12;
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uint64_t end = ((uint64_t)(1 + read32(mcc_tz_base + TZ_END(i)))) << 12;
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if (start) {
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start |= 0x0800000000;
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end |= 0x0800000000;
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start |= ram_base;
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end |= ram_base;
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printf("MMU: Unmapping TZ%d region at 0x%lx..0x%lx\n", i, start, end);
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mmu_rm_mapping(start, end - start);
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}
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@ -360,18 +362,19 @@ static void mmu_add_default_mappings(void)
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mmu_add_mapping(0x0680000000, 0x0680000000, 0x0020000000, MAIR_IDX_DEVICE_nGnRnE, PERM_RW_EL0);
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mmu_add_mapping(0x06a0000000, 0x06a0000000, 0x0060000000, MAIR_IDX_DEVICE_nGnRE, PERM_RW_EL0);
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uint64_t ram_size = cur_boot_args.mem_size + cur_boot_args.phys_base - 0x0800000000;
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ram_base = ALIGN_DOWN(cur_boot_args.phys_base, BIT(32));
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uint64_t ram_size = cur_boot_args.mem_size + cur_boot_args.phys_base - ram_base;
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ram_size = ALIGN_DOWN(ram_size, 0x4000);
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printf("MMU: Top of normal RAM: 0x%lx\n", 0x0800000000 + ram_size);
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printf("MMU: RAM base: 0x%lx\n", ram_base);
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printf("MMU: Top of normal RAM: 0x%lx\n", ram_base + ram_size);
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/*
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* Create identity mapping for RAM from 0x08_0000_0000
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* With SPRR enabled, this becomes RW.
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* This range includes all real RAM, including carveouts
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*/
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mmu_add_mapping(0x0800000000, 0x0800000000, cur_boot_args.mem_size_actual, MAIR_IDX_NORMAL,
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PERM_RWX);
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mmu_add_mapping(ram_base, ram_base, cur_boot_args.mem_size_actual, MAIR_IDX_NORMAL, PERM_RWX);
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/* Unmap carveout regions */
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mmu_unmap_carveouts();
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@ -398,22 +401,19 @@ static void mmu_add_default_mappings(void)
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* read/writable/exec by EL0 (but not executable by EL1)
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* With SPRR enabled, this becomes RX_EL0.
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*/
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mmu_add_mapping(0x0800000000 | REGION_RWX_EL0, 0x0800000000, ram_size, MAIR_IDX_NORMAL,
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PERM_RWX_EL0);
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mmu_add_mapping(ram_base | REGION_RWX_EL0, ram_base, ram_size, MAIR_IDX_NORMAL, PERM_RWX_EL0);
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/*
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* Create mapping for RAM from 0x98_0000_0000,
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* read/writable by EL0 (but not executable by EL1)
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* With SPRR enabled, this becomes RW_EL0.
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*/
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mmu_add_mapping(0x0800000000 | REGION_RW_EL0, 0x0800000000, ram_size, MAIR_IDX_NORMAL,
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PERM_RW_EL0);
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mmu_add_mapping(ram_base | REGION_RW_EL0, ram_base, ram_size, MAIR_IDX_NORMAL, PERM_RW_EL0);
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/*
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* Create mapping for RAM from 0xa8_0000_0000,
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* read/executable by EL1
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* This allows executing from dynamic regions in EL1
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*/
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mmu_add_mapping(0x0800000000 | REGION_RX_EL1, 0x0800000000, ram_size, MAIR_IDX_NORMAL,
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PERM_RX_EL0);
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mmu_add_mapping(ram_base | REGION_RX_EL1, ram_base, ram_size, MAIR_IDX_NORMAL, PERM_RX_EL0);
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/*
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* Create two seperate nGnRnE and nGnRE full mappings of MMIO space
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@ -7,8 +7,8 @@
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#include "types.h"
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#define REGION_RWX_EL0 0x8000000000
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#define REGION_RW_EL0 0x9000000000
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#define REGION_RX_EL1 0xa000000000
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#define REGION_RW_EL0 0xa000000000
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#define REGION_RX_EL1 0xc000000000
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/*
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* https://armv8-ref.codingbelief.com/en/chapter_d4/d43_2_armv8_translation_table_level_3_descriptor_formats.html
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@ -48,6 +48,8 @@
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#include "utils.h"
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extern uint64_t ram_base;
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void ic_ivau_range(void *addr, size_t length);
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void dc_ivac_range(void *addr, size_t length);
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void dc_zva_range(void *addr, size_t length);
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