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memory.c/h: fix typo SCTL -> SCTLR

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Signed-off-by: Sven Peter <sven@svenpeter.dev>
This commit is contained in:
Sven Peter 2021-01-23 21:40:13 +01:00 committed by Hector Martin
parent cbf4fbabd1
commit c9f975f886
2 changed files with 13 additions and 13 deletions
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14
src/memory.c
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@ -24,13 +24,13 @@ CACHE_RANGE_OP(dc_cvac_range, "dc cvac")
CACHE_RANGE_OP(dc_cvau_range, "dc cvau") CACHE_RANGE_OP(dc_cvau_range, "dc cvau")
CACHE_RANGE_OP(dc_civac_range, "dc civac") CACHE_RANGE_OP(dc_civac_range, "dc civac")
static inline uint64_t read_sctl(void) static inline uint64_t read_sctlr(void)
{ {
sysop("isb"); sysop("isb");
return mrs(SCTLR_EL2); return mrs(SCTLR_EL2);
} }
static inline void write_sctl(uint64_t val) static inline void write_sctlr(uint64_t val)
{ {
msr(SCTLR_EL2, val); msr(SCTLR_EL2, val);
sysop("isb"); sysop("isb");
@ -224,18 +224,18 @@ void mmu_init(void)
_mmu_add_default_mappings(); _mmu_add_default_mappings();
_mmu_configure(); _mmu_configure();
uint64_t sctl_old = read_sctl(); uint64_t sctlr_old = read_sctlr();
uint64_t sctl_new = sctl_old | SCTL_I | SCTL_C | SCTL_M; uint64_t sctlr_new = sctlr_old | SCTLR_I | SCTLR_C | SCTLR_M;
printf("MMU: SCTL_EL2: %x -> %x\n", sctl_old, sctl_new); printf("MMU: SCTLR_EL2: %x -> %x\n", sctlr_old, sctlr_new);
write_sctl(sctl_new); write_sctlr(sctlr_new);
printf("MMU: running with MMU and caches enabled!\n"); printf("MMU: running with MMU and caches enabled!\n");
} }
void mmu_shutdown(void) void mmu_shutdown(void)
{ {
printf("MMU: shutting down...\n"); printf("MMU: shutting down...\n");
write_sctl(read_sctl() & ~(SCTL_I | SCTL_C | SCTL_M)); write_sctlr(read_sctlr() & ~(SCTLR_I | SCTLR_C | SCTLR_M));
printf("MMU: shutdown successful, clearing caches\n"); printf("MMU: shutdown successful, clearing caches\n");
dcsw_op_all(DCSW_OP_DCCISW); dcsw_op_all(DCSW_OP_DCCISW);
} }

12
src/memory.h
View file

@ -15,13 +15,13 @@
/* /*
* https://developer.arm.com/docs/ddi0595/g/aarch64-system-registers/sctlr_el2 * https://developer.arm.com/docs/ddi0595/g/aarch64-system-registers/sctlr_el2
* SCTL_I enables instruction caches. * SCTLR_I enables instruction caches.
* SCTL_C enables data caches. * SCTLR_C enables data caches.
* SCTL_M enables the MMU. * SCTLR_M enables the MMU.
*/ */
#define SCTL_I (1UL << 12) #define SCTLR_I (1UL << 12)
#define SCTL_C (1UL << 2) #define SCTLR_C (1UL << 2)
#define SCTL_M (1UL) #define SCTLR_M (1UL)
/* /*
* https://developer.arm.com/documentation/100442/0100/register-descriptions/aarch64-system-registers/tcr-el2--translation-control-register--el2 * https://developer.arm.com/documentation/100442/0100/register-descriptions/aarch64-system-registers/tcr-el2--translation-control-register--el2