From c9f975f886b6de72cca937abd4eeb51315744e6d Mon Sep 17 00:00:00 2001 From: Sven Peter Date: Sat, 23 Jan 2021 21:40:13 +0100 Subject: [PATCH] memory.c/h: fix typo SCTL -> SCTLR Signed-off-by: Sven Peter --- src/memory.c | 14 +++++++------- src/memory.h | 12 ++++++------ 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/memory.c b/src/memory.c index cfe09e12..8fa539dd 100644 --- a/src/memory.c +++ b/src/memory.c @@ -24,13 +24,13 @@ CACHE_RANGE_OP(dc_cvac_range, "dc cvac") CACHE_RANGE_OP(dc_cvau_range, "dc cvau") CACHE_RANGE_OP(dc_civac_range, "dc civac") -static inline uint64_t read_sctl(void) +static inline uint64_t read_sctlr(void) { sysop("isb"); return mrs(SCTLR_EL2); } -static inline void write_sctl(uint64_t val) +static inline void write_sctlr(uint64_t val) { msr(SCTLR_EL2, val); sysop("isb"); @@ -224,18 +224,18 @@ void mmu_init(void) _mmu_add_default_mappings(); _mmu_configure(); - uint64_t sctl_old = read_sctl(); - uint64_t sctl_new = sctl_old | SCTL_I | SCTL_C | SCTL_M; + uint64_t sctlr_old = read_sctlr(); + uint64_t sctlr_new = sctlr_old | SCTLR_I | SCTLR_C | SCTLR_M; - printf("MMU: SCTL_EL2: %x -> %x\n", sctl_old, sctl_new); - write_sctl(sctl_new); + printf("MMU: SCTLR_EL2: %x -> %x\n", sctlr_old, sctlr_new); + write_sctlr(sctlr_new); printf("MMU: running with MMU and caches enabled!\n"); } void mmu_shutdown(void) { printf("MMU: shutting down...\n"); - write_sctl(read_sctl() & ~(SCTL_I | SCTL_C | SCTL_M)); + write_sctlr(read_sctlr() & ~(SCTLR_I | SCTLR_C | SCTLR_M)); printf("MMU: shutdown successful, clearing caches\n"); dcsw_op_all(DCSW_OP_DCCISW); } diff --git a/src/memory.h b/src/memory.h index e997b35f..905f64e8 100644 --- a/src/memory.h +++ b/src/memory.h @@ -15,13 +15,13 @@ /* * https://developer.arm.com/docs/ddi0595/g/aarch64-system-registers/sctlr_el2 - * SCTL_I enables instruction caches. - * SCTL_C enables data caches. - * SCTL_M enables the MMU. + * SCTLR_I enables instruction caches. + * SCTLR_C enables data caches. + * SCTLR_M enables the MMU. */ -#define SCTL_I (1UL << 12) -#define SCTL_C (1UL << 2) -#define SCTL_M (1UL) +#define SCTLR_I (1UL << 12) +#define SCTLR_C (1UL << 2) +#define SCTLR_M (1UL) /* * https://developer.arm.com/documentation/100442/0100/register-descriptions/aarch64-system-registers/tcr-el2--translation-control-register--el2