mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-21 22:23:05 +00:00
pcie: minimal initialization
Minimal initialization of the PCIe hardware such that the tunable can be applied such that they don't have to be passed along in the devicetree. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
This commit is contained in:
Mark Kettenis
Hector Martin
parent
570bfa1a17
commit
9604907b2d
4 changed files with 239 additions and 0 deletions
1
Makefile
1
Makefile
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@ -50,6 +50,7 @@ OBJECTS := \
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main.o \
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memory.o memory_asm.o \
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payload.o \
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pcie.o \
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pmgr.o \
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proxy.o \
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ringbuffer.o \
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@ -8,6 +8,7 @@
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#include "heapblock.h"
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#include "memory.h"
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#include "payload.h"
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#include "pcie.h"
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#include "pmgr.h"
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#include "smp.h"
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#include "string.h"
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@ -82,6 +83,7 @@ void m1n1_main(void)
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print_info();
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wdt_disable();
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pmgr_init();
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pcie_init();
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printf("Initialization complete.\n");
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228
src/pcie.c
Normal file
228
src/pcie.c
Normal file
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@ -0,0 +1,228 @@
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/* SPDX-License-Identifier: MIT */
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#include "adt.h"
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#include "pcie.h"
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#include "pmgr.h"
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#include "tunables.h"
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#include "utils.h"
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/*
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* The ADT uses 17 register sets:
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*
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* 0: 90000000 00000006 10000000 00000000 ECAM
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* 1: 80000000 00000006 00040000 00000000 RC
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* 2: 80080000 00000006 00090000 00000000 PHY
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* 3: 800c0000 00000006 00020000 00000000 PHY IP
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* 4: 8c000000 00000006 00004000 00000000 AXI
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* 5: 3d2bc000 00000000 00001000 00000000 fuses
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* 6: 81000000 00000006 00008000 00000000 port 0
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* 7: 81010000 00000006 00001000 00000000
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* 8: 80084000 00000006 00004000 00000000 port 0 PHY
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* 9: 800c8000 00000006 00016610 00000000
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* 10: 82000000 00000006 00008000 00000000 port 1
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* 11: 82010000 00000006 00001000 00000000
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* 12: 80088000 00000006 00004000 00000000 port 1 PHY
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* 13: 800d0000 00000006 00006000 00000000
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* 14: 83000000 00000006 00008000 00000000 port 2
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* 15: 83010000 00000006 00001000 00000000
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* 16: 8008c000 00000006 00004000 00000000 port 2 PHY
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* 17: 800d8000 00000006 00006000 00000000
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*/
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/* PHY registers */
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#define APCIE_PHY_CTRL 0x000
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#define APCIE_PHY_CTRL_CLK0REQ BIT(0)
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#define APCIE_PHY_CTRL_CLK1REQ BIT(1)
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#define APCIE_PHY_CTRL_CLK0ACK BIT(2)
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#define APCIE_PHY_CTRL_CLK1ACK BIT(3)
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#define APCIE_PHY_CTRL_RESET BIT(7)
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/* Port registers */
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#define APCIE_PORT_APPCLK 0x800
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#define APCIE_PORT_APPCLK_EN BIT(0)
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#define APCIE_PORT_STATUS 0x804
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#define APCIE_PORT_STATUS_RUN BIT(0)
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#define APCIE_PORT_RESET 0x814
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#define APCIE_PORT_RESET_DIS BIT(0)
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/* DesignWare PCIe Core registers */
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#define DWC_DBI_RO_WR 0x8bc
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#define DWC_DBI_RO_WR_EN BIT(0)
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struct fuse_bits {
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u16 src_reg;
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u16 tgt_reg;
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u8 src_bit;
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u8 tgt_bit;
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u8 width;
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};
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struct fuse_bits pcie_fuse_bits[] = {
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{0x0084, 0x6238, 4, 0, 6}, {0x0084, 0x6220, 10, 14, 3}, {0x0084, 0x62a4, 13, 17, 2},
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{0x0418, 0x522c, 27, 9, 2}, {0x0418, 0x522c, 13, 12, 3}, {0x0418, 0x5220, 18, 14, 3},
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{0x0418, 0x52a4, 21, 17, 2}, {0x0418, 0x522c, 23, 16, 5}, {0x0418, 0x5278, 23, 20, 3},
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{0x0418, 0x5018, 31, 2, 1}, {0x041c, 0x1204, 0, 2, 5}, {}};
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int pcie_init(void)
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{
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const char *path = "/arm-io/apcie";
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int adt_path[8];
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int adt_offset;
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adt_offset = adt_path_offset_trace(adt, path, adt_path);
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if (adt_offset < 0) {
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printf("pcie: Error getting node %s\n", path);
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return -1;
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}
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u64 config_base;
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if (adt_get_reg(adt, adt_path, "reg", 0, &config_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", 0, path);
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return -1;
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}
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u64 rc_base;
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if (adt_get_reg(adt, adt_path, "reg", 1, &rc_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", 1, path);
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return -1;
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}
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u64 phy_base;
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if (adt_get_reg(adt, adt_path, "reg", 2, &phy_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", 2, path);
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return -1;
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}
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u64 phy_ip_base;
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if (adt_get_reg(adt, adt_path, "reg", 3, &phy_ip_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", 3, path);
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return -1;
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}
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u64 fuse_base;
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if (adt_get_reg(adt, adt_path, "reg", 5, &fuse_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", 5, path);
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return -1;
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}
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if (pmgr_adt_clocks_enable(path)) {
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printf("pcie: Error enabling clocks for %s\n", path);
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return -1;
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}
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if (tunables_apply_local(path, "apcie-axi2af-tunables", 4)) {
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printf("pcie: Error applying %s for %s\n", "apcie-axi2af-tunables", path);
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return -1;
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}
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if (tunables_apply_local(path, "apcie-common-tunables", 1)) {
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printf("pcie: Error applying %s for %s\n", "apcie-common-tunables", path);
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return -1;
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}
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/*
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* Initialize PHY.
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*/
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if (tunables_apply_local(path, "apcie-phy-tunables", 2)) {
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printf("pcie: Error applying %s for %s\n", "apcie-phy-tunables", path);
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return -1;
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}
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set32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0REQ);
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if (poll32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK0ACK, APCIE_PHY_CTRL_CLK0ACK, 50000)) {
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printf("pcie: Timeout enabling PHY CLK0\n");
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return -1;
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}
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set32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK1REQ);
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if (poll32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_CLK1ACK, APCIE_PHY_CTRL_CLK1ACK, 50000)) {
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printf("pcie: Timeout enabling PHY CLK1\n");
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return -1;
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}
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clear32(phy_base + APCIE_PHY_CTRL, APCIE_PHY_CTRL_RESET);
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udelay(1);
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/* ??? */
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set32(rc_base + 0x24, 1);
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udelay(1);
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/* Apply "fuses". */
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for (int i = 0; pcie_fuse_bits[i].width; i++) {
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u32 fuse;
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fuse = (read32(fuse_base + pcie_fuse_bits[i].src_reg) >> pcie_fuse_bits[i].src_bit);
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mask32(phy_ip_base + pcie_fuse_bits[i].tgt_reg, (1 << pcie_fuse_bits[i].width) - 1,
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fuse << pcie_fuse_bits[i].tgt_bit);
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}
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if (tunables_apply_local(path, "apcie-phy-ip-pll-tunables", 3)) {
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printf("pcie: Error applying %s for %s\n", "apcie-phy-ip-pll-tunables", path);
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return -1;
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}
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if (tunables_apply_local(path, "apcie-phy-ip-auspma-tunables", 3)) {
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printf("pcie: Error applying %s for %s\n", "apcie-phy-ip-auspma-tunables", path);
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return -1;
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}
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int port;
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for (port = 0; port < 3; port++) {
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char bridge[64];
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/*
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* Initialize RC port.
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*/
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sprintf(bridge, "/arm-io/apcie/pci-bridge%d", port);
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u64 port_base;
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if (adt_get_reg(adt, adt_path, "reg", port * 4 + 6, &port_base, NULL)) {
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printf("pcie: Error getting reg with index %d for %s\n", port * 4 + 6, path);
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return -1;
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}
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if (tunables_apply_local_addr(bridge, "apcie-config-tunables", port_base)) {
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printf("pcie: Error applying %s for %s\n", "apcie-config-tunables", bridge);
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return -1;
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}
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set32(port_base + APCIE_PORT_APPCLK, APCIE_PORT_APPCLK_EN);
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/* PERSTN */
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set32(port_base + APCIE_PORT_RESET, APCIE_PORT_RESET_DIS);
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if (poll32(port_base + APCIE_PORT_STATUS, APCIE_PORT_STATUS_RUN, APCIE_PORT_STATUS_RUN,
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250000))
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return -1;
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/* Make Designware PCIe Core registers writable. */
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set32(config_base + DWC_DBI_RO_WR, DWC_DBI_RO_WR_EN);
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if (tunables_apply_local_addr(bridge, "pcie-rc-tunables", config_base)) {
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printf("pcie: Error applying %s for %s\n", "pcie-rc-tunables", bridge);
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return -1;
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}
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if (tunables_apply_local_addr(bridge, "pcie-rc-gen3-shadow-tunables", config_base)) {
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printf("pcie: Error applying %s for %s\n", "pcie-rc-gen3-shadow-tunables", bridge);
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return -1;
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}
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if (tunables_apply_local_addr(bridge, "pcie-rc-gen4-shadow-tunables", config_base)) {
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printf("pcie: Error applying %s for %s\n", "pcie-rc-gen4-shadow-tunables", bridge);
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return -1;
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}
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/* Make Designware PCIe Core registers readonly. */
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clear32(config_base + DWC_DBI_RO_WR, DWC_DBI_RO_WR_EN);
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/* Move to the next PCIe device on this bus. */
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config_base += (1 << 15);
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}
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printf("pcie: initialized.\n");
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return 0;
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}
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8
src/pcie.h
Normal file
8
src/pcie.h
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: MIT */
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#ifndef PCIE_H
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#define PCIE_H
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int pcie_init(void);
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#endif
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