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m1n1.hv: Make sysreg storage per-CPU

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Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin 2021-09-15 23:23:52 +09:00
parent 3871fa1e2f
commit 683161eef4
1 changed files with 3 additions and 3 deletions
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6
proxyclient/m1n1/hv.py
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@ -121,7 +121,7 @@ class HV(Reloadable):
self._bps = [None, None, None, None, None]
self.sym_offset = 0
self.symbols = []
self.sysreg = {}
self.sysreg = {0: {}}
self.novm = False
self._in_handler = False
self._sigint_pending = False
@ -549,7 +549,7 @@ class HV(Reloadable):
value = 0
if enc in shadow:
if iss.DIR == MSR_DIR.READ:
value = self.sysreg.setdefault(enc, 0)
value = self.sysreg[self.ctx.cpu_id].setdefault(enc, 0)
self.log(f"Shadow: mrs x{iss.Rt}, {name} = {value:x}")
if iss.Rt != 31:
ctx.regs[iss.Rt] = value
@ -557,7 +557,7 @@ class HV(Reloadable):
if iss.Rt != 31:
value = ctx.regs[iss.Rt]
self.log(f"Shadow: msr {name}, x{iss.Rt} = {value:x}")
self.sysreg[enc] = value
self.sysreg[self.ctx.cpu_id][enc] = value
elif enc in skip or (enc in ro and iss.DIR == MSR_DIR.WRITE):
if iss.DIR == MSR_DIR.READ:
self.log(f"Skip: mrs x{iss.Rt}, {name} = 0")