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https://github.com/AsahiLinux/m1n1
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m1n1.hv: Add hv.log() that prepends CPU index, use it
Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin
parent
56b54a6641
commit
3871fa1e2f
1 changed files with 33 additions and 27 deletions
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@ -155,6 +155,12 @@ class HV(Reloadable):
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if callable(a):
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self.shell_locals[attr] = getattr(self, attr)
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def log(self, s, *args, **kwargs):
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if self.ctx is not None:
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print(f"[cpu{self.ctx.cpu_id}] " + s, *args, **kwargs)
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else:
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print(s, *args, **kwargs)
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def unmap(self, ipa, size):
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assert self.p.hv_map(ipa, 0, size, 0) >= 0
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@ -544,26 +550,26 @@ class HV(Reloadable):
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if enc in shadow:
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if iss.DIR == MSR_DIR.READ:
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value = self.sysreg.setdefault(enc, 0)
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print(f"Shadow: mrs x{iss.Rt}, {name} = {value:x}")
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self.log(f"Shadow: mrs x{iss.Rt}, {name} = {value:x}")
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if iss.Rt != 31:
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ctx.regs[iss.Rt] = value
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else:
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if iss.Rt != 31:
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value = ctx.regs[iss.Rt]
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print(f"Shadow: msr {name}, x{iss.Rt} = {value:x}")
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self.log(f"Shadow: msr {name}, x{iss.Rt} = {value:x}")
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self.sysreg[enc] = value
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elif enc in skip or (enc in ro and iss.DIR == MSR_DIR.WRITE):
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if iss.DIR == MSR_DIR.READ:
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print(f"Skip: mrs x{iss.Rt}, {name} = 0")
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self.log(f"Skip: mrs x{iss.Rt}, {name} = 0")
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if iss.Rt != 31:
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ctx.regs[iss.Rt] = 0
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else:
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if iss.Rt != 31:
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value = ctx.regs[iss.Rt]
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print(f"Skip: msr {name}, x{iss.Rt} = {value:x}")
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self.log(f"Skip: msr {name}, x{iss.Rt} = {value:x}")
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else:
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if iss.DIR == MSR_DIR.READ:
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print(f"Pass: mrs x{iss.Rt}, {name}", end=" ")
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self.log(f"Pass: mrs x{iss.Rt}, {name}", end=" ")
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sys.stdout.flush()
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enc2 = self.MSR_REDIRECTS.get(enc, enc)
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value = self.u.mrs(enc2)
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@ -573,7 +579,7 @@ class HV(Reloadable):
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else:
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if iss.Rt != 31:
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value = ctx.regs[iss.Rt]
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print(f"Pass: msr {name}, x{iss.Rt} = {value:x}", end=" ")
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self.log(f"Pass: msr {name}, x{iss.Rt} = {value:x}", end=" ")
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enc2 = self.MSR_REDIRECTS.get(enc, enc)
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sys.stdout.flush()
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self.u.msr(enc2, value, call=self.p.gl2_call)
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@ -595,7 +601,7 @@ class HV(Reloadable):
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c = ARMAsm(".inst " + ",".join(str(i) for i in code), ctx.elr_phys)
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insn = "; ".join(c.disassemble())
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print(f"IMPDEF exception on: {insn}")
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self.log(f"IMPDEF exception on: {insn}")
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return False
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@ -606,7 +612,7 @@ class HV(Reloadable):
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vector, target = self.vectors[idx]
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if target is None:
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print(f"EL1: Exception #{vector} with no target")
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self.log(f"EL1: Exception #{vector} with no target")
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target = 0
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ok = False
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else:
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@ -625,22 +631,22 @@ class HV(Reloadable):
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if esr.EC == ESR_EC.DABORT or esr.EC == ESR_EC.IABORT:
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far = self.u.mrs(FAR_EL12)
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if self.sym(elr)[1] != "com.apple.kernel:_panic_trap_to_debugger":
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print("Page fault")
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self.log("Page fault")
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return ok
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print(f"EL1: Exception #{vector} ({esr.EC!s}) to {self.addr(target)} from {spsr.M.name}")
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print(f" ELR={self.addr(elr)} (0x{elr_phys:x})")
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print(f" SP_EL1=0x{sp_el1:x} SP_EL0=0x{sp_el0:x}")
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self.log(f"EL1: Exception #{vector} ({esr.EC!s}) to {self.addr(target)} from {spsr.M.name}")
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self.log(f" ELR={self.addr(elr)} (0x{elr_phys:x})")
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self.log(f" SP_EL1=0x{sp_el1:x} SP_EL0=0x{sp_el0:x}")
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if far is not None:
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print(f" FAR={self.addr(far)}")
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self.log(f" FAR={self.addr(far)}")
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if elr_phys:
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self.u.disassemble_at(elr_phys - 4 * 4, 9 * 4, elr_phys)
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if self.sym(elr)[1] == "com.apple.kernel:_panic_trap_to_debugger":
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print("Panic! Trying to decode panic...")
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self.log("Panic! Trying to decode panic...")
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try:
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self.decode_panic_call()
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except:
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print("Error decoding panic.")
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self.log("Error decoding panic.")
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try:
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self.bt()
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except:
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@ -649,11 +655,11 @@ class HV(Reloadable):
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if esr.EC == ESR_EC.UNKNOWN:
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instr = self.p.read32(elr_phys)
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if instr == 0xe7ffdeff:
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print("Debugger break! Trying to decode panic...")
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self.log("Debugger break! Trying to decode panic...")
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try:
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self.decode_dbg_panic()
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except:
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print("Error decoding panic.")
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self.log("Error decoding panic.")
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try:
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self.bt()
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except:
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@ -662,7 +668,7 @@ class HV(Reloadable):
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return False
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else:
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elr = self.u.mrs(ELR_EL12)
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print(f"Guest: {str(EXC(vector & 3))} at {self.addr(elr)}")
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self.log(f"Guest: {str(EXC(vector & 3))} at {self.addr(elr)}")
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return ok
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@ -730,15 +736,15 @@ class HV(Reloadable):
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elif code == HV_EVENT.USER_INTERRUPT:
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handled = True
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except Exception as e:
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print(f"Python exception while handling guest exception:")
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self.log(f"Python exception while handling guest exception:")
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traceback.print_exc()
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if handled:
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ret = EXC_RET.HANDLED
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if self._sigint_pending:
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print("User interrupt")
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self.log("User interrupt")
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else:
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print(f"Guest exception: {reason.name}/{code.name}")
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self.log(f"Guest exception: {reason.name}/{code.name}")
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self.u.print_exception(code, ctx)
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if self._sigint_pending or not handled:
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@ -852,14 +858,14 @@ class HV(Reloadable):
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if self.u.mrs(SCTLR_EL12) & 1:
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vbar_phys = self.p.hv_translate(vbar, False, False)
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if vbar_phys == 0:
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print(f"VBAR vaddr 0x{vbar:x} translation failed!")
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self.log(f"VBAR vaddr 0x{vbar:x} translation failed!")
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if self.vbar_el1 is not None:
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self.want_vbar = vbar
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self.u.msr(VBAR_EL12, self.vbar_el1)
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return
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else:
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if vbar & (1 << 63):
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print(f"VBAR vaddr 0x{vbar:x} without translation enabled")
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self.log(f"VBAR vaddr 0x{vbar:x} without translation enabled")
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if self.vbar_el1 is not None:
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self.want_vbar = vbar
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self.u.msr(VBAR_EL12, self.vbar_el1)
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@ -871,7 +877,7 @@ class HV(Reloadable):
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self.want_vbar = None
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self.u.msr(VBAR_EL12, vbar)
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print(f"New VBAR paddr: 0x{vbar_phys:x}")
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self.log(f"New VBAR paddr: 0x{vbar_phys:x}")
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#for i in range(16):
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for i in [0, 3, 4, 7, 8, 11, 12, 15]:
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@ -879,17 +885,17 @@ class HV(Reloadable):
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addr = vbar_phys + 0x80 * i
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orig = self.p.read32(addr)
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if (orig & 0xfc000000) != 0x14000000:
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print(f"Unknown vector #{i}:\n")
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self.log(f"Unknown vector #{i}:\n")
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self.u.disassemble_at(addr, 16)
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else:
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idx = len(self.vectors)
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delta = orig & 0x3ffffff
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if delta == 0:
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target = None
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print(f"Vector #{i}: Loop\n")
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self.log(f"Vector #{i}: Loop\n")
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else:
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target = (delta << 2) + vbar + 0x80 * i
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print(f"Vector #{i}: 0x{target:x}\n")
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self.log(f"Vector #{i}: 0x{target:x}\n")
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self.vectors.append((i, target))
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self.u.disassemble_at(addr, 16)
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self.p.write32(addr, self.hvc(idx))
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