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https://github.com/AsahiLinux/m1n1
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m1n1.hw.codecs.cs42l84: Extend register definitions
Signed-off-by: Martin Povišer <povik@protonmail.com>
This commit is contained in:
Martin Povišer
Hector Martin
parent
42f7f46bdc
commit
4f6a65f481
1 changed files with 179 additions and 28 deletions
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@ -1,4 +1,4 @@
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from m1n1.utils import Register8, Register32, RegMap, irange
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from m1n1.utils import Register8, Register16, Register32, RegMap, irange
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from enum import IntEnum
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class R_IRQ_MASK1(Register8):
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@ -7,6 +7,9 @@ class R_IRQ_MASK1(Register8):
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TIP_PLUG = 2
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TIP_UNPLUG = 3
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class R_IRQ_MASK3(Register8):
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HSDET_AUTO_DONE = 7
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class E_DCID_GND_SEL(IntEnum):
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NONE = 0
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HS3 = 1
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@ -52,6 +55,19 @@ class R_TR_SENSE_STATUS(Register8):
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TIP_PLUG = 2
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TIP_UNPLUG = 3
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class R_HS_DET_STATUS2(Register8):
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HS_TRUE = 1
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SHORT_TRUE = 0
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class R_MSM_BLOCK_EN1(Register8):
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pass
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class R_MSM_BLOCK_EN2(Register8):
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ASP_EN = 6
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BUS_EN = 5
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DAC_EN = 4
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ADC_EN = 3
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class R_MSM_BLOCK_EN3(Register8):
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TR_SENSE_EN = 3
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DCID_EN = 4
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@ -71,13 +87,67 @@ class E_SAMP_RATE(IntEnum):
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S_88K2HZ = 13
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S_176K4HZ = 14
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class E_MCLK_SRC(IntEnum):
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RCO = 0b00
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MCLK_PIN = 0b01
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BCLK = 0b10
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PLL = 0b11
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class E_MCLK_FREQ(IntEnum):
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F_12MHZ = 0b00
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F_24MHZ = 0b01
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F_12_288KHZ = 0b10
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F_24_576KHZ = 0b11
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class R_CCM_CTRL1(Register8):
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MCLK_SRC = 1, 0, E_MCLK_SRC
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MCLK_FREQ = 3, 2, E_MCLK_FREQ
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class E_REFCLK_DIV(IntEnum):
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DIV1 = 0b00
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DIV2 = 0b01
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DIV4 = 0b10
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DIV8 = 0b11
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class R_CCM_CTRL3(Register8):
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REFCLK_DIV = 2, 1, E_REFCLK_DIV
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REFCLK_IS_MCLK = 0 # BLCK otherwise
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class R_CCM_CTRL4(Register8):
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REFCLK_EN = 0
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class R_CCM_SAMP_RATE(Register8):
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RATE = 7, 0, E_SAMP_RATE
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class E_PLL_MODE(IntEnum):
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UNSUPP = 0b00
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BYPASS_512 = 0b01
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BYPASS_1024 = 0b10
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BYPASS_BOTH = 0b11
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class R_PLL_CTRL(Register8):
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MODE = 2, 1, E_PLL_MODE
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EN = 0
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class E_WNF_CF(IntEnum):
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F_UNK = 0b00
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F_300HZ = 0b11
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class R_ADC_CTRL1(Register8):
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PREAMP_GAIN = 7, 6
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PGA_GAIN = 5, 0
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class R_ADC_CTRL4(Register8): # maybe
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WNF_CF = 5, 4, E_WNF_CF
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WNF_EN = 3
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class R_DAC_CTRL1(Register8):
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UNMUTE = 0
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HP_LOAD = 2 # maybe
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UNK1 = 3
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UNK2 = 4
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UNK3 = 5 # always set
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UNK3 = 5
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HIGH_V = 6
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class E_PULLDOWN_R(IntEnum):
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@ -88,8 +158,39 @@ class E_PULLDOWN_R(IntEnum):
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class R_DAC_CTRL2(Register8):
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PULLDOWN_R = 3, 0, E_PULLDOWN_R
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class R_HP_VOL_CTRL(Register8):
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ZERO_CROSS = 1
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SOFT = 0
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class E_BUS_SOURCE(IntEnum):
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EMPTY = 0b0000
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ADC = 0b0111
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ASP_RX_CH1 = 0b1101
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ASP_RX_CH2 = 0b1110
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class R_BUS_DAC_SRC(Register8):
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CHB = 7, 4, E_BUS_SOURCE
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CHA = 3, 0, E_BUS_SOURCE
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class R_BUS_ASP_TX_SRC(Register8):
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CH2 = 7, 4, E_BUS_SOURCE
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CH1 = 3, 0, E_BUS_SOURCE
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class E_HSBIAS_SENSE_TRIP(IntEnum):
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C_12UA = 0b000
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C_23UA = 0b001
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C_41UA = 0b010
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C_52UA = 0b011
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C_64UA = 0b100
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C_75UA = 0b101
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C_93UA = 0b110
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C_104UA = 0b111
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class R_HSBIAS_SC_AUTOCTL(Register8):
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HSBIAS_SENSE_EN = 7
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AUTO_HSBIAS_HIZ = 6
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TIP_SENSE_EN = 5
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SENSE_TRIP = 2, 0, E_HSBIAS_SENSE_TRIP
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class E_TIP_SENSE_CTRL(IntEnum):
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DISABLED = 0b00
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@ -100,6 +201,11 @@ class R_TIP_SENSE_CTRL2(Register8):
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CTRL = 7, 6, E_TIP_SENSE_CTRL
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INV = 5
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class E_HSBIAS_DET_MODE(IntEnum):
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DISABLED = 0b00
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SHORT_DET = 0b01
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NORMAL = 0b11
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class E_HSBIAS_CTRL(IntEnum):
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HI_Z = 0b00
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U_0V0 = 0b01
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@ -107,7 +213,10 @@ class E_HSBIAS_CTRL(IntEnum):
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U_2V7 = 0b11
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class R_MISC_DET_CTRL(Register8):
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UNK1 = 7
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DETECT_MODE = 4, 3, E_HSBIAS_DET_MODE
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HSBIAS_CTRL = 2, 1, E_HSBIAS_CTRL
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PDN_MIC_LVL_DET = 0
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class E_S0_DEBOUNCE_TIME(IntEnum):
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T_10MS = 0b000
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@ -125,6 +234,12 @@ class R_MIC_DET_CTRL2(Register8):
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class R_MIC_DET_CTRL4(Register8):
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LATCH_TO_VP = 1
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class R_HS_DET_CTRL2(Register8):
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CTRL = 7, 6
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SET = 5, 4
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REF = 3
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AUTO_TIME = 1, 0
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class R_HS_SWITCH_CTRL(Register8):
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REF_HS3 = 7
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REF_HS4 = 6
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@ -135,22 +250,50 @@ class R_HS_SWITCH_CTRL(Register8):
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GNDHS_HS3 = 1
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GNDHS_HS4 = 0
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class R_ASP_CTRL(Register8):
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TDM_MODE = 2
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BCLK_EN = 1
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class R_ASP_FSYNC_CTRL23(Register16):
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BCLK_PERIOD = 12, 1
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class R_ASP_TX_HIZ_DLY_CTRL(Register8):
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DRV_Z = 5, 4
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HIZ_DELAY = 3, 2
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FS = 1
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UNK1 = 0
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class R_ASP_RX_EN(Register8):
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CH2_EN = 1
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CH1_EN = 0
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class R_ASP_CH_CTRL(Register32):
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WIDTH = 23, 16
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SLOT_START = 10, 1
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EDGE = 0 # set for rising edge
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class CS42L84Regs(RegMap):
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DEVID = irange(0x0, 5), Register8
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FREEZE = 0x6, Register8
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SW_RESET = 0x203, Register8
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IRQ_STATUS = irange(0x400, 3), Register8
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IRQ_STATUS1 = 0x400, R_IRQ_MASK1
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IRQ_STATUS2 = 0x401, Register8
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IRQ_STATUS3 = 0x402, R_IRQ_MASK3
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PLL_LOCK_STATUS = 0x40e, Register8 # bit 0x10
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IRQ_MASK1 = 0x418, R_IRQ_MASK1
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IRQ_MASK2 = 0x419, Register8
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IRQ_MASK3 = 0x41a, Register8
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IRQ_MASK3 = 0x41a, R_IRQ_MASK3
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CCM_CTRL = irange(0x600, 4), Register8
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CCM_CTRL1 = 0x600, R_CCM_CTRL1
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CCM_SAMP_RATE = 0x601, R_CCM_SAMP_RATE
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CCM_CTRL3 = 0x602, R_CCM_CTRL3
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CCM_CTRL4 = 0x603, R_CCM_CTRL4
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CCM_ASP_CLK_CTRL = 0x608, Register8
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PLL_CTRL = 0x800, Register8
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PLL_CTRL = 0x800, R_PLL_CTRL
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PLL_DIV_FRAC = irange(0x804, 3), Register8
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PLL_DIV_INT = 0x807, Register8
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PLL_DIVOUT = 0x808, Register8
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@ -173,20 +316,29 @@ class CS42L84Regs(RegMap):
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TR_SENSE_STATUS = 0x1288, R_TR_SENSE_STATUS
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HSBIAS_SC_AUTOCTL = 0x1470, R_HSBIAS_SC_AUTOCTL
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WAKE_CTRL = 0x1471, Register8 # guess (cs42l42)
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TIP_SENSE_CTRL2 = 0x1473, R_TIP_SENSE_CTRL2 # guess (cs42l42)
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MISC_DET_CTRL = 0x1474, R_MISC_DET_CTRL # guess (cs42l42)
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WAKE_CTRL = 0x1471, Register8
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TIP_SENSE_CTRL2 = 0x1473, R_TIP_SENSE_CTRL2
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MISC_DET_CTRL = 0x1474, R_MISC_DET_CTRL
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MIC_DET_CTRL2 = 0x1478, R_MIC_DET_CTRL2
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MIC_DET_CTRL4 = 0x1477, R_MIC_DET_CTRL4
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MIKEY_DET_STATUS = irange(0x147c, 2), Register8
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MIKEY_DET_IRQ_MASK = irange(0x1480, 2), Register8
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MIKEY_DET_IRQ_STATUS = irange(0x1484, 2), Register8
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HS_DET_STATUS1 = 0x147c, Register8
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HS_DET_STATUS2 = 0x147d, R_HS_DET_STATUS2
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HS_DET_IRQ_MASK = irange(0x1480, 2), Register8
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HS_DET_IRQ_STATUS = irange(0x1484, 2), Register8
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MSM_BLOCK_EN1 = 0x1800, R_MSM_BLOCK_EN1
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MSM_BLOCK_EN2 = 0x1801, R_MSM_BLOCK_EN2
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MSM_BLOCK_EN3 = 0x1802, R_MSM_BLOCK_EN3
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HS_DET_CTRL1 = 0x1810, Register8
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HS_DET_CTRL2 = 0x1811, R_HS_DET_CTRL2
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HS_SWITCH_CTRL = 0x1812, R_HS_SWITCH_CTRL
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HS_CLAMP_DISABLE = 0x1813, R_HS_CLAMP_DISABLE
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ADC_CTRL = irange(0x2000, 4), Register8
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ADC_CTRL1 = 0x2000, R_ADC_CTRL1
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ADC_CTRL2 = 0x2001, Register8 # volume
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ADC_CTRL3 = 0x2002, Register8
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ADC_CTRL4 = 0x2003, R_ADC_CTRL4
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DAC_CTRL1 = 0x3000, R_DAC_CTRL1
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DAC_CTRL2 = 0x3001, R_DAC_CTRL2
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@ -194,21 +346,20 @@ class CS42L84Regs(RegMap):
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DACA_VOL_MSB = 0x3005, Register8 # sign bit
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DACB_VOL_LSB = 0x3006, Register8
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DACB_VOL_MSB = 0x3007, Register8 # sign bit
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HP_VOL_CTRL = 0x3020, Register8
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HP_VOL_CTRL = 0x3020, R_HP_VOL_CTRL
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HP_CLAMP_CTRL = 0x3123, Register8
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ASP_CTRL = 0x5000, Register8
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ASP_FSYNC_CTRL = irange(0x500f, 3), Register8
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ASP_DATA_CTRL = 0x5018, Register8
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BUS_ASP_TX_SRC = 0x4000, R_BUS_ASP_TX_SRC
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BUS_DAC_SRC = 0x4001, R_BUS_DAC_SRC
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ASP_RX_EN = 0x5020, Register8
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ASP_CTRL = 0x5000, R_ASP_CTRL
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ASP_FSYNC_CTRL23 = 0x5010, R_ASP_FSYNC_CTRL23
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ASP_DATA_CTRL = 0x5018, R_ASP_TX_HIZ_DLY_CTRL
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ASP_RX_EN = 0x5020, R_ASP_RX_EN
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ASP_TX_EN = 0x5024, Register8
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ASP_RXSLOT_CH1_LSB = 0x5028, Register8
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ASP_RXSLOT_CH1_MSB = 0x5029, Register8
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ASP_RXSLOT_CH2_LSB = 0x502c, Register8
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ASP_RXSLOT_CH2_MSB = 0x502d, Register8
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ASP_TXSLOT_CH1_LSB = 0x5068, Register8
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ASP_TXSLOT_CH1_MSB = 0x5068, Register8
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ASP_RX1_CTRL = 0x5028, R_ASP_CH_CTRL # 32bit
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ASP_RX2_CTRL = 0x502c, R_ASP_CH_CTRL # 32bit
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ASP_TX1_CTRL = 0x5068, R_ASP_CH_CTRL
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ASP_TX2_CTRL = 0x506c, R_ASP_CH_CTRL
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