diff --git a/proxyclient/m1n1/hw/codecs/cs42l84.py b/proxyclient/m1n1/hw/codecs/cs42l84.py index d433a266..095b4216 100644 --- a/proxyclient/m1n1/hw/codecs/cs42l84.py +++ b/proxyclient/m1n1/hw/codecs/cs42l84.py @@ -1,4 +1,4 @@ -from m1n1.utils import Register8, Register32, RegMap, irange +from m1n1.utils import Register8, Register16, Register32, RegMap, irange from enum import IntEnum class R_IRQ_MASK1(Register8): @@ -7,6 +7,9 @@ class R_IRQ_MASK1(Register8): TIP_PLUG = 2 TIP_UNPLUG = 3 +class R_IRQ_MASK3(Register8): + HSDET_AUTO_DONE = 7 + class E_DCID_GND_SEL(IntEnum): NONE = 0 HS3 = 1 @@ -52,6 +55,19 @@ class R_TR_SENSE_STATUS(Register8): TIP_PLUG = 2 TIP_UNPLUG = 3 +class R_HS_DET_STATUS2(Register8): + HS_TRUE = 1 + SHORT_TRUE = 0 + +class R_MSM_BLOCK_EN1(Register8): + pass + +class R_MSM_BLOCK_EN2(Register8): + ASP_EN = 6 + BUS_EN = 5 + DAC_EN = 4 + ADC_EN = 3 + class R_MSM_BLOCK_EN3(Register8): TR_SENSE_EN = 3 DCID_EN = 4 @@ -71,13 +87,67 @@ class E_SAMP_RATE(IntEnum): S_88K2HZ = 13 S_176K4HZ = 14 +class E_MCLK_SRC(IntEnum): + RCO = 0b00 + MCLK_PIN = 0b01 + BCLK = 0b10 + PLL = 0b11 + +class E_MCLK_FREQ(IntEnum): + F_12MHZ = 0b00 + F_24MHZ = 0b01 + F_12_288KHZ = 0b10 + F_24_576KHZ = 0b11 + +class R_CCM_CTRL1(Register8): + MCLK_SRC = 1, 0, E_MCLK_SRC + MCLK_FREQ = 3, 2, E_MCLK_FREQ + +class E_REFCLK_DIV(IntEnum): + DIV1 = 0b00 + DIV2 = 0b01 + DIV4 = 0b10 + DIV8 = 0b11 + +class R_CCM_CTRL3(Register8): + REFCLK_DIV = 2, 1, E_REFCLK_DIV + REFCLK_IS_MCLK = 0 # BLCK otherwise + +class R_CCM_CTRL4(Register8): + REFCLK_EN = 0 + class R_CCM_SAMP_RATE(Register8): RATE = 7, 0, E_SAMP_RATE +class E_PLL_MODE(IntEnum): + UNSUPP = 0b00 + BYPASS_512 = 0b01 + BYPASS_1024 = 0b10 + BYPASS_BOTH = 0b11 + +class R_PLL_CTRL(Register8): + MODE = 2, 1, E_PLL_MODE + EN = 0 + +class E_WNF_CF(IntEnum): + F_UNK = 0b00 + F_300HZ = 0b11 + +class R_ADC_CTRL1(Register8): + PREAMP_GAIN = 7, 6 + PGA_GAIN = 5, 0 + +class R_ADC_CTRL4(Register8): # maybe + WNF_CF = 5, 4, E_WNF_CF + WNF_EN = 3 + class R_DAC_CTRL1(Register8): + UNMUTE = 0 + HP_LOAD = 2 # maybe + UNK1 = 3 UNK2 = 4 - UNK3 = 5 # always set + UNK3 = 5 HIGH_V = 6 class E_PULLDOWN_R(IntEnum): @@ -88,8 +158,39 @@ class E_PULLDOWN_R(IntEnum): class R_DAC_CTRL2(Register8): PULLDOWN_R = 3, 0, E_PULLDOWN_R +class R_HP_VOL_CTRL(Register8): + ZERO_CROSS = 1 + SOFT = 0 + +class E_BUS_SOURCE(IntEnum): + EMPTY = 0b0000 + ADC = 0b0111 + ASP_RX_CH1 = 0b1101 + ASP_RX_CH2 = 0b1110 + +class R_BUS_DAC_SRC(Register8): + CHB = 7, 4, E_BUS_SOURCE + CHA = 3, 0, E_BUS_SOURCE + +class R_BUS_ASP_TX_SRC(Register8): + CH2 = 7, 4, E_BUS_SOURCE + CH1 = 3, 0, E_BUS_SOURCE + +class E_HSBIAS_SENSE_TRIP(IntEnum): + C_12UA = 0b000 + C_23UA = 0b001 + C_41UA = 0b010 + C_52UA = 0b011 + C_64UA = 0b100 + C_75UA = 0b101 + C_93UA = 0b110 + C_104UA = 0b111 + class R_HSBIAS_SC_AUTOCTL(Register8): - TIP_SENSE_EN = 5 + HSBIAS_SENSE_EN = 7 + AUTO_HSBIAS_HIZ = 6 + TIP_SENSE_EN = 5 + SENSE_TRIP = 2, 0, E_HSBIAS_SENSE_TRIP class E_TIP_SENSE_CTRL(IntEnum): DISABLED = 0b00 @@ -100,6 +201,11 @@ class R_TIP_SENSE_CTRL2(Register8): CTRL = 7, 6, E_TIP_SENSE_CTRL INV = 5 +class E_HSBIAS_DET_MODE(IntEnum): + DISABLED = 0b00 + SHORT_DET = 0b01 + NORMAL = 0b11 + class E_HSBIAS_CTRL(IntEnum): HI_Z = 0b00 U_0V0 = 0b01 @@ -107,7 +213,10 @@ class E_HSBIAS_CTRL(IntEnum): U_2V7 = 0b11 class R_MISC_DET_CTRL(Register8): - HSBIAS_CTRL = 2, 1, E_HSBIAS_CTRL + UNK1 = 7 + DETECT_MODE = 4, 3, E_HSBIAS_DET_MODE + HSBIAS_CTRL = 2, 1, E_HSBIAS_CTRL + PDN_MIC_LVL_DET = 0 class E_S0_DEBOUNCE_TIME(IntEnum): T_10MS = 0b000 @@ -125,6 +234,12 @@ class R_MIC_DET_CTRL2(Register8): class R_MIC_DET_CTRL4(Register8): LATCH_TO_VP = 1 +class R_HS_DET_CTRL2(Register8): + CTRL = 7, 6 + SET = 5, 4 + REF = 3 + AUTO_TIME = 1, 0 + class R_HS_SWITCH_CTRL(Register8): REF_HS3 = 7 REF_HS4 = 6 @@ -135,22 +250,50 @@ class R_HS_SWITCH_CTRL(Register8): GNDHS_HS3 = 1 GNDHS_HS4 = 0 +class R_ASP_CTRL(Register8): + TDM_MODE = 2 + BCLK_EN = 1 + +class R_ASP_FSYNC_CTRL23(Register16): + BCLK_PERIOD = 12, 1 + +class R_ASP_TX_HIZ_DLY_CTRL(Register8): + DRV_Z = 5, 4 + HIZ_DELAY = 3, 2 + FS = 1 + UNK1 = 0 + +class R_ASP_RX_EN(Register8): + CH2_EN = 1 + CH1_EN = 0 + +class R_ASP_CH_CTRL(Register32): + WIDTH = 23, 16 + SLOT_START = 10, 1 + EDGE = 0 # set for rising edge + class CS42L84Regs(RegMap): DEVID = irange(0x0, 5), Register8 FREEZE = 0x6, Register8 SW_RESET = 0x203, Register8 - IRQ_STATUS = irange(0x400, 3), Register8 + IRQ_STATUS1 = 0x400, R_IRQ_MASK1 + IRQ_STATUS2 = 0x401, Register8 + IRQ_STATUS3 = 0x402, R_IRQ_MASK3 + PLL_LOCK_STATUS = 0x40e, Register8 # bit 0x10 + IRQ_MASK1 = 0x418, R_IRQ_MASK1 IRQ_MASK2 = 0x419, Register8 - IRQ_MASK3 = 0x41a, Register8 + IRQ_MASK3 = 0x41a, R_IRQ_MASK3 - CCM_CTRL = irange(0x600, 4), Register8 + CCM_CTRL1 = 0x600, R_CCM_CTRL1 CCM_SAMP_RATE = 0x601, R_CCM_SAMP_RATE + CCM_CTRL3 = 0x602, R_CCM_CTRL3 + CCM_CTRL4 = 0x603, R_CCM_CTRL4 CCM_ASP_CLK_CTRL = 0x608, Register8 - PLL_CTRL = 0x800, Register8 + PLL_CTRL = 0x800, R_PLL_CTRL PLL_DIV_FRAC = irange(0x804, 3), Register8 PLL_DIV_INT = 0x807, Register8 PLL_DIVOUT = 0x808, Register8 @@ -173,20 +316,29 @@ class CS42L84Regs(RegMap): TR_SENSE_STATUS = 0x1288, R_TR_SENSE_STATUS HSBIAS_SC_AUTOCTL = 0x1470, R_HSBIAS_SC_AUTOCTL - WAKE_CTRL = 0x1471, Register8 # guess (cs42l42) - TIP_SENSE_CTRL2 = 0x1473, R_TIP_SENSE_CTRL2 # guess (cs42l42) - MISC_DET_CTRL = 0x1474, R_MISC_DET_CTRL # guess (cs42l42) + WAKE_CTRL = 0x1471, Register8 + TIP_SENSE_CTRL2 = 0x1473, R_TIP_SENSE_CTRL2 + MISC_DET_CTRL = 0x1474, R_MISC_DET_CTRL MIC_DET_CTRL2 = 0x1478, R_MIC_DET_CTRL2 MIC_DET_CTRL4 = 0x1477, R_MIC_DET_CTRL4 - MIKEY_DET_STATUS = irange(0x147c, 2), Register8 - MIKEY_DET_IRQ_MASK = irange(0x1480, 2), Register8 - MIKEY_DET_IRQ_STATUS = irange(0x1484, 2), Register8 + HS_DET_STATUS1 = 0x147c, Register8 + HS_DET_STATUS2 = 0x147d, R_HS_DET_STATUS2 + HS_DET_IRQ_MASK = irange(0x1480, 2), Register8 + HS_DET_IRQ_STATUS = irange(0x1484, 2), Register8 + MSM_BLOCK_EN1 = 0x1800, R_MSM_BLOCK_EN1 + MSM_BLOCK_EN2 = 0x1801, R_MSM_BLOCK_EN2 MSM_BLOCK_EN3 = 0x1802, R_MSM_BLOCK_EN3 + + HS_DET_CTRL1 = 0x1810, Register8 + HS_DET_CTRL2 = 0x1811, R_HS_DET_CTRL2 HS_SWITCH_CTRL = 0x1812, R_HS_SWITCH_CTRL HS_CLAMP_DISABLE = 0x1813, R_HS_CLAMP_DISABLE - ADC_CTRL = irange(0x2000, 4), Register8 + ADC_CTRL1 = 0x2000, R_ADC_CTRL1 + ADC_CTRL2 = 0x2001, Register8 # volume + ADC_CTRL3 = 0x2002, Register8 + ADC_CTRL4 = 0x2003, R_ADC_CTRL4 DAC_CTRL1 = 0x3000, R_DAC_CTRL1 DAC_CTRL2 = 0x3001, R_DAC_CTRL2 @@ -194,21 +346,20 @@ class CS42L84Regs(RegMap): DACA_VOL_MSB = 0x3005, Register8 # sign bit DACB_VOL_LSB = 0x3006, Register8 DACB_VOL_MSB = 0x3007, Register8 # sign bit - HP_VOL_CTRL = 0x3020, Register8 + HP_VOL_CTRL = 0x3020, R_HP_VOL_CTRL HP_CLAMP_CTRL = 0x3123, Register8 - ASP_CTRL = 0x5000, Register8 - ASP_FSYNC_CTRL = irange(0x500f, 3), Register8 - ASP_DATA_CTRL = 0x5018, Register8 + BUS_ASP_TX_SRC = 0x4000, R_BUS_ASP_TX_SRC + BUS_DAC_SRC = 0x4001, R_BUS_DAC_SRC - ASP_RX_EN = 0x5020, Register8 + ASP_CTRL = 0x5000, R_ASP_CTRL + ASP_FSYNC_CTRL23 = 0x5010, R_ASP_FSYNC_CTRL23 + ASP_DATA_CTRL = 0x5018, R_ASP_TX_HIZ_DLY_CTRL + + ASP_RX_EN = 0x5020, R_ASP_RX_EN ASP_TX_EN = 0x5024, Register8 - ASP_RXSLOT_CH1_LSB = 0x5028, Register8 - ASP_RXSLOT_CH1_MSB = 0x5029, Register8 - - ASP_RXSLOT_CH2_LSB = 0x502c, Register8 - ASP_RXSLOT_CH2_MSB = 0x502d, Register8 - - ASP_TXSLOT_CH1_LSB = 0x5068, Register8 - ASP_TXSLOT_CH1_MSB = 0x5068, Register8 + ASP_RX1_CTRL = 0x5028, R_ASP_CH_CTRL # 32bit + ASP_RX2_CTRL = 0x502c, R_ASP_CH_CTRL # 32bit + ASP_TX1_CTRL = 0x5068, R_ASP_CH_CTRL + ASP_TX2_CTRL = 0x506c, R_ASP_CH_CTRL