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https://github.com/AsahiLinux/m1n1
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MMU: add cache operations by set/way
this embeds a slightly modified file taken from arm-trusted-firmware. Signed-off-by: Sven Peter <sven@svenpeter.dev>
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5 changed files with 204 additions and 1 deletions
26
3rdparty_licenses/LICENSE.BSD-3.arm
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26
3rdparty_licenses/LICENSE.BSD-3.arm
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@ -0,0 +1,26 @@
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Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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- Neither the name of Arm nor the names of its contributors may be used to
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endorse or promote products derived from this software without specific
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prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2
Makefile
2
Makefile
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@ -17,7 +17,7 @@ TINF_OBJECTS := $(patsubst %,tinf/%, \
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adler32.o crc32.o tinfgzip.o tinflate.o tinfzlib.o)
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OBJECTS := adt.o bootlogo_128.o bootlogo_256.o chickens.o exception.o exception_asm.o fb.o \
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main.o memory.o proxy.o smp.o start.o startup.o string.o uart.o uartproxy.o utils.o \
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main.o memory.o memory_asm.o proxy.o smp.o start.o startup.o string.o uart.o uartproxy.o utils.o \
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utils_asm.o vsprintf.o $(MINILZLIB_OBJECTS) $(TINF_OBJECTS)
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DTS := apple-j274.dts
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@ -32,3 +32,9 @@ m1n1 embeds a slightly modified version of [tinf](https://github.com/jibsen/tinf
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[ZLIB](3rdparty_licenses/LICENSE.tinf) licensed and copyright:
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* Copyright (c) 2003-2019 Joergen Ibsen
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m1n1 embeds portions taken from
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[arm-trusted-firwmare](https://github.com/ARM-software/arm-trusted-firmware), which is
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[BSD](3rdparty_licenses/LICENSE.BSD-3.arm) licensed and copyright:
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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@ -12,6 +12,11 @@ void dc_cvac_range(void *addr, size_t length);
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void dc_cvau_range(void *addr, size_t length);
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void dc_civac_range(void *addr, size_t length);
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#define DCSW_OP_DCISW 0x0
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#define DCSW_OP_DCCISW 0x1
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#define DCSW_OP_DCCSW 0x2
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void dcsw_op_all(u64 op_type);
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void mmu_init(void);
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void mmu_shutdown(void);
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#endif
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166
src/memory_asm.S
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166
src/memory_asm.S
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/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define LOC_SHIFT 24
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#define CLIDR_FIELD_WIDTH 3
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#define LEVEL_SHIFT 1
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.macro func, name
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.globl \name
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.type \name, @function
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\name:
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.endm
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.globl dcsw_op_all
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/*
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* This macro can be used for implementing various data cache operations `op`
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*/
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.macro do_dcache_maintenance_by_mva op
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/* Exit early if size is zero */
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cbz x1, exit_loop_\op
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dcache_line_size x2, x3
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add x1, x0, x1
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sub x3, x2, #1
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bic x0, x0, x3
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loop_\op:
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dc \op, x0
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add x0, x0, x2
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cmp x0, x1
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b.lo loop_\op
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dsb sy
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exit_loop_\op:
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ret
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.endm
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/* ---------------------------------------------------------------
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* Data cache operations by set/way to the level specified
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*
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* The main function, do_dcsw_op requires:
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* x0: The operation type (0-2), as defined in arch.h
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* x3: The last cache level to operate on
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* x9: clidr_el1
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* x10: The cache level to begin operation from
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* and will carry out the operation on each data cache from level 0
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* to the level in x3 in sequence
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*
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* The dcsw_op macro sets up the x3 and x9 parameters based on
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* clidr_el1 cache information before invoking the main function
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* ---------------------------------------------------------------
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*/
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.macro dcsw_op shift, fw, ls
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mrs x9, clidr_el1
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ubfx x3, x9, \shift, \fw
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lsl x3, x3, \ls
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mov x10, xzr
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b do_dcsw_op
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.endm
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func do_dcsw_op
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cbz x3, exit
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adr x14, dcsw_loop_table // compute inner loop address
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add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions
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mov x0, x9
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mov w8, #1
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loop1:
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add x2, x10, x10, lsr #1 // work out 3x current cache level
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lsr x1, x0, x2 // extract cache type bits from clidr
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and x1, x1, #7 // mask the bits for current cache only
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cmp x1, #2 // see what cache we have at this level
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b.lo level_done // nothing to do if no cache or icache
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msr csselr_el1, x10 // select current cache level in csselr
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isb // isb to sych the new cssr&csidr
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mrs x1, ccsidr_el1 // read the new ccsidr
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and x2, x1, #7 // extract the length of the cache lines
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add x2, x2, #4 // add 4 (line length offset)
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ubfx x4, x1, #3, #10 // maximum way number
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clz w5, w4 // bit position of way size increment
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lsl w9, w4, w5 // w9 = aligned max way number
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lsl w16, w8, w5 // w16 = way number loop decrement
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orr w9, w10, w9 // w9 = combine way and cache number
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ubfx w6, w1, #13, #15 // w6 = max set number
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lsl w17, w8, w2 // w17 = set number loop decrement
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dsb sy // barrier before we start this level
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br x14 // jump to DC operation specific loop
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.macro dcsw_loop _op
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loop2_\_op:
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lsl w7, w6, w2 // w7 = aligned max set number
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loop3_\_op:
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orr w11, w9, w7 // combine cache, way and set number
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dc \_op, x11
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subs w7, w7, w17 // decrement set number
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b.hs loop3_\_op
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subs x9, x9, x16 // decrement way number
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b.hs loop2_\_op
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b level_done
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.endm
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level_done:
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add x10, x10, #2 // increment cache number
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cmp x3, x10
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b.hi loop1
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msr csselr_el1, xzr // select cache level 0 in csselr
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dsb sy // barrier to complete final cache operation
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isb
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exit:
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ret
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dcsw_loop_table:
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dcsw_loop isw
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dcsw_loop cisw
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dcsw_loop csw
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func dcsw_op_all
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dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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/* ---------------------------------------------------------------
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* Helper macro for data cache operations by set/way for the
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* level specified
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* ---------------------------------------------------------------
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*/
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.macro dcsw_op_level level
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mrs x9, clidr_el1
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mov x3, \level
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sub x10, x3, #2
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b do_dcsw_op
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.endm
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 1 cache
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*
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* The main function, do_dcsw_op requires:
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* x0: The operation type (0-2), as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level1
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dcsw_op_level #(1 << LEVEL_SHIFT)
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 2 cache
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*
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* The main function, do_dcsw_op requires:
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* x0: The operation type (0-2), as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level2
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dcsw_op_level #(2 << LEVEL_SHIFT)
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 3 cache
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*
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* The main function, do_dcsw_op requires:
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* x0: The operation type (0-2), as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level3
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dcsw_op_level #(3 << LEVEL_SHIFT)
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