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https://github.com/AsahiLinux/m1n1
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MMU: add initial support
Signed-off-by: Sven Peter <sven@svenpeter.dev>
This commit is contained in:
Sven Peter
Hector Martin
parent
63fad7e3e2
commit
f244919c98
3 changed files with 289 additions and 0 deletions
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@ -4,6 +4,7 @@
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#include "adt.h"
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#include "fb.h"
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#include "memory.h"
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#include "smp.h"
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#include "string.h"
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#include "uart.h"
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@ -69,6 +70,7 @@ void m1n1_main(void)
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printf("Licensed under the MIT license\n\n");
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printf("Running in EL%d\n\n", mrs(CurrentEL) >> 2);
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mmu_init();
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#ifdef SHOW_LOGO
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fb_init();
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285
src/memory.c
285
src/memory.c
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@ -3,6 +3,7 @@
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#include "memory.h"
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#include "utils.h"
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#define PAGE_SIZE 0x4000
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#define CACHE_LINE_SIZE 64
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#define CACHE_RANGE_OP(func, op) \
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@ -22,3 +23,287 @@ CACHE_RANGE_OP(dc_zva_range, "dc zva")
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CACHE_RANGE_OP(dc_cvac_range, "dc cvac")
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CACHE_RANGE_OP(dc_cvau_range, "dc cvau")
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CACHE_RANGE_OP(dc_civac_range, "dc civac")
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static inline u64 read_sctlr(void)
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{
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sysop("isb");
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return mrs(SCTLR_EL2);
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}
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static inline void write_sctlr(u64 val)
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{
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msr(SCTLR_EL2, val);
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sysop("isb");
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}
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/*
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* https://armv8-ref.codingbelief.com/en/chapter_d4/d43_2_armv8_translation_table_level_3_descriptor_formats.html
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* PTE_TYPE_BLOCK indicates that the page table entry (PTE) points to a physical memory block
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* PTE_TYPE_TABLE indicates that the PTE points to another PTE
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* PTE_FLAG_ACCESS is required to allow access to the memory region
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* PTE_MAIR_INDEX sets the MAIR index to be used for this PTE
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*/
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#define PTE_TYPE_BLOCK 0b01
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#define PTE_TYPE_TABLE 0b11
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#define PTE_FLAG_ACCESS (1 << 10)
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#define PTE_MAIR_INDEX(i) ((i & 7) << 2)
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/*
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* https://developer.arm.com/docs/ddi0595/g/aarch64-system-registers/sctlr_el2
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* SCTLR_I enables instruction caches.
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* SCTLR_C enables data caches.
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* SCTLR_M enables the MMU.
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*/
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#define SCTLR_I (1UL << 12)
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#define SCTLR_C (1UL << 2)
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#define SCTLR_M (1UL)
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/*
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* https://developer.arm.com/docs/ddi0595/h/aarch64-system-registers/tcr_el2
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* TCR_IPS_1TB selects 40 bits/1TB intermediate physical address size
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* TCR_PS_1TB selects 40 bits/1TB physical address size
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* TCR_TG0_16K selects 16K pages
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* TCR_SH0_IS marks memory used during translation table walks as inner sharable
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* TCR_ORGN0_WBWA and TCR_IRGN0_WBWA set the cacheability atrributes for memory
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* used during translation table walks to Inner/Outer
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* Write-Back Read-Allocate Write-Allocate Cacheable
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* TCR_T0SZ_48BIT selects 48bit virtual addresses
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*/
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#define TCR_IPS_1TB ((0b010UL) << 32)
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#define TCR_PS_1TB ((0b010UL) << 16)
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#define TCR_TG0_16K ((0b10UL) << 14)
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#define TCR_SH0_IS ((0b11UL) << 12)
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#define TCR_ORGN0_WBWA ((0b01UL) << 10)
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#define TCR_IRGN0_WBWA ((0b01UL) << 8)
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#define TCR_T0SZ_48BIT ((16UL) << 0)
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/*
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* aarch64 allows to configure attribute sets for up to eight different memory
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* types. we need normal memory and two types of device memory (nGnRnE and
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* nGnRE) in m1n1.
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* The indexes here are selected arbitrarily: A page table entry
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* contains a field to select one of these which will then be used
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* to select the corresponding memory access flags from MAIR.
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*/
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#define MAIR_INDEX_NORMAL 0
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#define MAIR_INDEX_DEVICE_nGnRnE 1
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#define MAIR_INDEX_DEVICE_nGnRE 2
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#define MAIR_SHIFT_NORMAL (MAIR_INDEX_NORMAL * 8)
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#define MAIR_SHIFT_DEVICE_nGnRnE (MAIR_INDEX_DEVICE_nGnRnE * 8)
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#define MAIR_SHIFT_DEVICE_nGnRE (MAIR_INDEX_DEVICE_nGnRE * 8)
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/*
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* https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/memory-attribute-indirection-register--el1
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*
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* MAIR_ATTR_NORMAL_DEFAULT sets Normal Memory, Outer Write-back non-transient,
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* Inner Write-back non-transient, R=1, W=1
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* MAIR_ATTR_DEVICE_nGnRnE sets Device-nGnRnE memory
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* MAIR_ATTR_DEVICE_nGnRE sets Device-nGnRE memory
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*/
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#define MAIR_ATTR_NORMAL_DEFAULT 0xffUL
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#define MAIR_ATTR_DEVICE_nGnRnE 0x00UL
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#define MAIR_ATTR_DEVICE_nGnRE 0x04UL
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/*
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* We want use 16KB pages which would usually result in the following
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* virtual address space:
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*
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* [L0 index] [L1 index] [L2 index] [L3 index] [page offset]
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* 1 bit 11 bits 11 bits 11 bits 14 bits
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*
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* To simplify things we only allow 32MB mappings directly from
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* the L2 tables such that in m1n1 all virtual addresses will look like this
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* instead (Block maps from L0 or L1 are not possible with 16KB pages):
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*
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* [L0 index] [L1 index] [L2 index] [page offset]
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* 1 bit 11 bits 11 bits 25 bits
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*
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* We initalize two L1 tables which cover the entire virtual memory space,
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* point to them in the singe L0 table and then create L2 tables on demand.
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*/
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#define VADDR_PAGE_OFFSET_BITS 25
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#define VADDR_L2_INDEX_BITS 11
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#define VADDR_L1_INDEX_BITS 11
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#define VADDR_L0_INDEX_BITS 1
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#define MAX_L2_TABLES 10
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#define ENTRIES_PER_TABLE 2048
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#define L2_PAGE_SIZE 0x2000000
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static u64 pagetable_L0[2] ALIGNED(PAGE_SIZE);
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static u64 pagetable_L1[2][ENTRIES_PER_TABLE] ALIGNED(PAGE_SIZE);
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static u64 pagetable_L2[MAX_L2_TABLES][ENTRIES_PER_TABLE] ALIGNED(PAGE_SIZE);
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static u32 pagetable_L2_next = 0;
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static u64 mmu_make_block_pte(uintptr_t addr, u8 attribute_index)
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{
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u64 pte = PTE_TYPE_BLOCK;
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pte |= addr;
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pte |= PTE_FLAG_ACCESS;
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pte |= PTE_MAIR_INDEX(attribute_index);
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return pte;
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}
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static u64 mmu_make_table_pte(u64 *addr)
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{
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u64 pte = PTE_TYPE_TABLE;
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pte |= (uintptr_t)addr;
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pte |= PTE_FLAG_ACCESS;
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return pte;
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}
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static void mmu_init_pagetables(void)
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{
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memset64(pagetable_L0, 0, sizeof pagetable_L0);
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memset64(pagetable_L1, 0, sizeof pagetable_L1);
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memset64(pagetable_L2, 0, sizeof pagetable_L2);
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pagetable_L0[0] = mmu_make_table_pte(&pagetable_L1[0][0]);
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pagetable_L0[1] = mmu_make_table_pte(&pagetable_L1[1][0]);
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}
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static u8 mmu_extract_L0_index(uintptr_t addr)
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{
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addr >>= VADDR_PAGE_OFFSET_BITS;
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addr >>= VADDR_L2_INDEX_BITS;
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addr >>= VADDR_L1_INDEX_BITS;
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addr &= (1 << VADDR_L0_INDEX_BITS) - 1;
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return (u8)addr;
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}
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static u64 mmu_extract_L1_index(uintptr_t addr)
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{
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addr >>= VADDR_PAGE_OFFSET_BITS;
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addr >>= VADDR_L2_INDEX_BITS;
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addr &= (1 << VADDR_L1_INDEX_BITS) - 1;
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return (u64)addr;
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}
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static u64 mmu_extract_L2_index(uintptr_t addr)
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{
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addr >>= VADDR_PAGE_OFFSET_BITS;
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addr &= (1 << VADDR_L2_INDEX_BITS) - 1;
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return (u64)addr;
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}
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static uintptr_t mmu_extract_addr(u64 pte)
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{
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/*
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* https://armv8-ref.codingbelief.com/en/chapter_d4/d43_1_vmsav8-64_translation_table_descriptor_formats.html
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* need to extract bits [47:14]
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*/
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pte &= ((1ULL << 48) - 1);
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pte &= ~((1ULL << 14) - 1);
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return (uintptr_t)pte;
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}
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static u64 *mmu_get_L1_table(uintptr_t addr)
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{
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return pagetable_L1[mmu_extract_L0_index(addr)];
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}
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static u64 *mmu_get_L2_table(uintptr_t addr)
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{
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u64 *tbl_l1 = mmu_get_L1_table(addr);
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u64 l1_idx = mmu_extract_L1_index(addr);
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u64 desc_l1 = tbl_l1[l1_idx];
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if (desc_l1 == 0) {
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if (pagetable_L2_next == MAX_L2_TABLES)
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panic("MMU: not enough space to create an additional L2 table to "
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"map %lx",
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addr);
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desc_l1 = mmu_make_table_pte((u64 *)&pagetable_L2[pagetable_L2_next++]);
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tbl_l1[l1_idx] = desc_l1;
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}
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return (u64 *)mmu_extract_addr(desc_l1);
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}
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static void mmu_add_single_mapping(uintptr_t from, uintptr_t to, u8 attribute_index)
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{
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u64 *tbl_l2 = mmu_get_L2_table(from);
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u64 l2_idx = mmu_extract_L2_index(from);
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if (tbl_l2[l2_idx])
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panic("MMU: mapping for %lx already exists", from);
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tbl_l2[l2_idx] = mmu_make_block_pte(to, attribute_index);
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}
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static void mmu_add_mapping(uintptr_t from, uintptr_t to, size_t size, u8 attribute_index)
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{
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if (from % L2_PAGE_SIZE)
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panic("mmu_add_mapping: from address not aligned: %lx", from);
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if (to % L2_PAGE_SIZE)
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panic("mmu_add_mapping: to address not aligned: %lx", to);
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if (size % L2_PAGE_SIZE)
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panic("mmu_add_mapping: size not aligned: %lx", size);
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while (size > 0) {
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mmu_add_single_mapping(from, to, attribute_index);
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from += L2_PAGE_SIZE;
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to += L2_PAGE_SIZE;
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size -= L2_PAGE_SIZE;
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}
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}
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static void mmu_add_default_mappings(void)
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{
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/*
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* create MMIO mapping as both nGnRnE (identity) and nGnRE (starting at
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* 0xf0_0000_0000)
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*/
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mmu_add_mapping(0x0000000000, 0x0000000000, 0x0800000000, MAIR_INDEX_DEVICE_nGnRnE);
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mmu_add_mapping(0xf000000000, 0x0000000000, 0x0800000000, MAIR_INDEX_DEVICE_nGnRE);
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/*
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* create identity mapping for 16GB RAM from 0x08_0000_0000 to
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* 0x0c_0000_0000
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*/
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mmu_add_mapping(0x0800000000, 0x0800000000, 0x0400000000, MAIR_INDEX_NORMAL);
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}
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static void mmu_configure(void)
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{
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msr(MAIR_EL2, (MAIR_ATTR_NORMAL_DEFAULT << MAIR_SHIFT_NORMAL) |
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(MAIR_ATTR_DEVICE_nGnRnE << MAIR_SHIFT_DEVICE_nGnRnE) |
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(MAIR_ATTR_DEVICE_nGnRE << MAIR_SHIFT_DEVICE_nGnRE));
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msr(TCR_EL2,
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TCR_TG0_16K | TCR_IPS_1TB | TCR_SH0_IS | TCR_ORGN0_WBWA | TCR_IRGN0_WBWA | TCR_T0SZ_48BIT);
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msr(TTBR0_EL2, (uintptr_t)pagetable_L0);
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// Armv8-A Address Translation, 100940_0101_en, page 28
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sysop("dsb ishst");
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sysop("tlbi vmalls12e1is");
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sysop("dsb ish");
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sysop("isb");
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}
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void mmu_init(void)
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{
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printf("MMU: Initializing...\n");
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mmu_init_pagetables();
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mmu_add_default_mappings();
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mmu_configure();
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u64 sctlr_old = read_sctlr();
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u64 sctlr_new = sctlr_old | SCTLR_I | SCTLR_C | SCTLR_M;
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printf("MMU: SCTLR_EL2: %x -> %x\n", sctlr_old, sctlr_new);
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write_sctlr(sctlr_new);
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printf("MMU: running with MMU and caches enabled!\n");
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}
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void mmu_shutdown(void)
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{
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// FIXME: do we need to flush caches here?
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printf("MMU: shutting down...\n");
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write_sctlr(read_sctlr() & ~(SCTLR_I | SCTLR_C | SCTLR_M));
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printf("MMU: shutdown successful.\n");
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}
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@ -12,4 +12,6 @@ void dc_cvac_range(void *addr, size_t length);
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void dc_cvau_range(void *addr, size_t length);
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void dc_civac_range(void *addr, size_t length);
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void mmu_init(void);
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void mmu_shutdown(void);
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#endif
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