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dcp/afk: Read mailbox in afk_epic_rx
This is primarily to aid the dcp tracer to report received messages in the order m1n1's implementation actually reads them. This unfortunately only works for the dptx-port endpoint and not for the dcp/iboot endpoint. Signed-off-by: Janne Grunau <j@jannau.net>
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parent
c1f14a4738
commit
26ceac4a3a
1 changed files with 19 additions and 5 deletions
24
src/afk.c
24
src/afk.c
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@ -156,12 +156,12 @@ bool afk_rb_init(afk_epic_ep_t *epic, struct afk_rb *rb, u64 base, u64 size)
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return true;
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}
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static int afk_epic_poll(afk_epic_t *afk, int endpoint)
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static int afk_epic_poll(afk_epic_t *afk, int endpoint, u32 count)
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{
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int ret;
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struct rtkit_message msg;
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while ((ret = rtkit_recv(afk->rtk, &msg)) == 0)
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while (count-- > 0 && (ret = rtkit_recv(afk->rtk, &msg)) == 0)
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;
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if (ret < 0) {
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@ -169,6 +169,11 @@ static int afk_epic_poll(afk_epic_t *afk, int endpoint)
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return ret;
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}
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if (ret == 0) {
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printf("EPIC: rtkit_recv timed out!\n");
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return -1;
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}
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if (msg.ep < 0x20 || msg.ep >= 0x30 || !afk->endpoint[msg.ep - 0x20]) {
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printf("EPIC: received message for unexpected endpoint %d\n", msg.ep);
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return 0;
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@ -260,9 +265,18 @@ static int afk_epic_rx(afk_epic_ep_t *epic, struct afk_qe **qe)
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u32 rptr = rb->hdr->rptr;
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if (epic->ep == 0x2a && rptr != rb->hdr->wptr) {
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bool can_read = rtkit_can_recv(epic->afk->rtk);
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if (can_read) {
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ret = afk_epic_poll(epic->afk, epic->ep, 1);
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if (ret < 0)
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return ret;
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}
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}
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while (rptr == rb->hdr->wptr) {
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do {
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ret = afk_epic_poll(epic->afk, epic->ep);
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ret = afk_epic_poll(epic->afk, epic->ep, UINT32_MAX);
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if (ret < 0)
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return ret;
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} while (ret == 0);
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@ -618,7 +632,7 @@ afk_epic_ep_t *afk_epic_start_ep(afk_epic_t *afk, int endpoint, bool notify)
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}
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while (!epic->started) {
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int ret = afk_epic_poll(epic->afk, endpoint);
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int ret = afk_epic_poll(epic->afk, endpoint, UINT32_MAX);
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if (ret < 0)
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break;
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else if (ret > 0)
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@ -642,7 +656,7 @@ int afk_epic_shutdown_ep(afk_epic_ep_t *epic)
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}
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while (epic->started) {
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int ret = afk_epic_poll(epic->afk, epic->ep);
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int ret = afk_epic_poll(epic->afk, epic->ep, UINT32_MAX);
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if (ret < 0)
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break;
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}
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